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1 for more information www.linear.com/lt8311 typical application features description synchronous rectifier controller with opto-coupler driver for forward converters the lt ? 8311 is used on the secondary side of a forward converter to provide synchronous mosfet control and output voltage feedback through an opto-coupler. the lt8311s unique preactive mode allows control of the secondary-side mosfets without requiring a traditional pulse transformer for primary- to secondary-side com - munication. in preactive mode, the output inductor current operates in discontinuous conduction mode ( dcm) at light load. if forced continuous mode ( fcm) operation is desired at light load, the lt8311 can, alternatively, be used in sync mode, where a pulse transformer is required to send synchronous control signals from the primary-side ic to the lt8311. the lt8311 offers a full featured opto-coupler controller, incorporating a 1.5% reference, a transconductance error amplifier and a 10 ma opto-driver. power good monitoring and output soft-start/overshoot control are also included. the lt8311 is available in a 16- lead fe package with pins removed for high voltage spacing requirements. 18v to 72v, 12v/8a active clamp isolated forward converter applications n wide input supply range: 3.7v to 30v n preactive mode: n no pulse transformer required n dcm operation at light load n sync mode: n fcm or dcm operation at light load n achieves highest efficiency n 1.5% feedback voltage reference n 10ma opto-coupler driver n output power good indicator n integrated soft-start function n offline and hv car battery isolated power supplies n 48v isolated power supplies n industrial, automotive and military systems l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 8311 ta01 lt3753 uvlo_vsec ovlo ivsec rt tos tblnk tao tas gnd ss1 ss2 intv cc aout fb sync s out 71.5k 1f 0.47f 4.7f 3 v in 18v to 72v v in 100k 5.9k 1.82k 31.6k 240khz 34k comp isensen oc out isensep 49.9k 2.2f 100v ?? 100nf 4.7f 2k 6m 100 1f 1k 100k 100k 124k lt8311 fsw csw csp cg csn opto gnd comp sync pmode ss fb v in intv cc pgood timer v out 12v v out 6.8h 1.78k 1.5k fg 2k 100k 20k 11.3k 22f 2 2k 1.78k 470f 68pf 15nf 2.94k 1f 4.7f 2.2f 2.2nf 10k 100nf 4:4 100k 2.2nf 10pf + lt 8311 8311f
2 for more information www.linear.com/lt8311 table of contents features ............................................................................................................................ 1 applications ....................................................................................................................... 1 t ypical application ............................................................................................................... 1 description ......................................................................................................................... 1 absolute maximum ratings ..................................................................................................... 3 order information ................................................................................................................. 3 pin configuration ................................................................................................................. 3 electrical characteristics ........................................................................................................ 4 t ypical performance characteristics .......................................................................................... 7 pin functions ..................................................................................................................... 11 block diagram .................................................................................................................... 12 operation ..........................................................................................................................13 fundamentals of forward converter operation in ccm ..................................................................... 13 lt8311 synchronous control schemes ..................................................................................................... 17 preactive mode synchronous control .................................................................................................... 17 sync mode synchronous control ............................................................................................................. 19 op to-coupler control ............................................................................................................................... ... 21 applications information ....................................................................................................... 25 v in bias supply .................................................................................................................................................. 25 intv cc bias supply ............................................................................................................................................ 26 lt8311 op to control fundamentals ........................................................................................................... 27 l t8311 synchronous control fundamentals .......................................................................................... 31 preactive mode synchronous control ................................................................................................... 37 sync mode synchronous control ............................................................................................................ 38 t ypical applications ............................................................................................................. 40 package description ............................................................................................................ 47 t ypical application .............................................................................................................. 48 related parts ..................................................................................................................... 48 lt 8311 8311f
3 for more information www.linear.com/lt8311 pin configuration absolute maximum ratings csw, fsw, csp ....................................... C 0.3 v to 150 v sync ........................................................... C12 v to 12 v v in , pgood ................................................ C0. 3 v to 30 v intv cc , pmode ......................................... C0. 3 v to 18 v fb , ss , comp ........................................... C 0.3 v to 2.5 v timer ....................................................... C 0.3 v to 1.5 v csn ........................................................... C 0.3 v to 0.4 v opto , timer short - circuit current d uration .................................... in finite ( note 5) operating junction temperature range lt 8 311 e ( n otes 2, 3) ......................... C 40 c to 125 c lt 83 11 i ( notes 2, 3) .......................... C 40 c to 125 c lt 83 11 h ( notes 2, 3) ......................... C 40 c to 150 c lt 83 11 mp ( notes 2, 3) ...................... C 55 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ).................... 300 c (note 1) fe package 20-lead plastic tssop 1 3 5 6 7 8 9 10 top view 20 18 16 15 14 13 12 11 csw fsw fg intv cc v in pmode opto comp csp csn cg sync ss pgood timer fb 21 gnd ja = 38c/w, jc = 10c/w exposed pad ( pin 21) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8311efe#pbf lt8311efe#trpbf lt8311fe 20-lead plastic tssop C40c to 125c lt8311ife#pbf lt8311ife#trpbf lt8311fe 20-lead plastic tssop C40c to 125c lt8311hfe#pbf lt8311hfe#trpbf lt8311fe 20-lead plastic tssop C40c to 150c lt8311mpfe#pbf lt8311mpfe#trpbf lt8311fe 20-lead plastic tssop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ lt 8311 8311f
4 for more information www.linear.com/lt8311 electrical characteristics parameter conditions min typ max units supply v in operating range l 3.7 30 v v in uvlo v in rising hysteresis l 50 3.6 100 3.7 150 v mv quiescent current not switching 4.5 5.5 ma error amplifier feedback reference voltage v in = 12v l 1.209 1.227 1.245 v feedback voltage line regulation 3.7v v in 30v, % of fb ref voltage 0.015 0.1 % feedback voltage load regulation 1.3v comp 1.8v, % of fb ref voltage 0.05 0.1 % feedback pin bias current current out of fb pin 120 200 na error amplifier transconductance 1.3v comp 1.8v 370 mhos error amplifier voltage gain 1.3v comp 1.8v 65 db error amplifier output swing high fb = 1v 1.9 2.3 2.8 v error amplifier output swing low fb = 1.5v 0.75 1 1.25 v power good power not good ( outside this window ) % relative to fb ref voltage 4 10 16 % power good (inside this window) % relative to fb ref voltage 7 % power good indicator wait time minimum time that fb must stay within power good window before pgood pin goes low 175 s power good leakage pgood = 30v 1 a power good output low voltage current into pgood pin = 1ma l 0.2 0.3 v soft-start (ss) ss wake-up slew current current exists upon part wake up, shuts off after ss wake up offset voltage is satisfied (note 6) 1 ma ss wake-up offset voltage v fb C v ss , upon part wake up ss is slewed up to an offset voltage below fb by ss wake-up slew current 16 mv ss charge current ss = 0v, fb = 0.6v (note 9) l 9 10 11 a ss pull-down amplifier offset voltage v ss C v fb , pull-down amplifier prevents ss from rising beyond this offset voltage above fb when the fb pin voltage is below 50% of the fb reference voltage 100 mv ss pull-down amplifier maximum sink current ss = 1.5v, fb = 0.6v (note 7) 13 ma ss high clamp voltage 1.8 2 v opto driver comp buffer input offset voltage 1.3v comp (note 5) 0.9 v opto-driver reference voltage (note 5) 1 v opto-driver dc gain (note 5) C7 v/ v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, v intvcc = 8v, pmode = 5v, c cg = c fg = 100pf, unless otherwise noted. (note 2) lt 8311 8311f
5 for more information www.linear.com/lt8311 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, v intvcc = 8v, pmode = 5v, c cg = c fg = 100pf, unless otherwise noted. (note 2) parameter conditions min typ max units inverting dc gain from comp pin to opto pin (?v opto /?v comp ), 1.290v comp 1.310v C5 v/ v (?v opto /?v comp ), 1.490v comp 1.510v C5.9 v/ v (?v opto /?v comp ), 1.890v comp 1.910v C6.2 v/ v opto-driver C3db bandwidth no load (note 5) 400 khz opto-driver output swing low fb = 1v, comp = ss = opto = open l 0.5 0.85 v opto-driver output swing high v in = 3.7v, fb = 1.5v, comp = ss = open, i opto = 10ma l v in C 1.7 v in C 1.4 v v in = 30v, fb = 1.5v, comp = ss = open, i opto = 10ma l 5.2 6.5 v opto- driver output short- circuit current v in = 30v, fb = 1.5v, comp = ss = open, opto = 0v (note 6) l 10.5 15 18 ma opto-driver output sink current fb = 1v, opto = 1.2v (note 7) l 200 300 420 a internal linear regulator intv cc regulation voltage no load l 6.5 7 7.5 v intv cc load regulation (?v intvcc /?i intvcc ), 0a i intvcc 20ma 1.8 3 mv/ma intv cc uvlo rising l 4.6 4.8 v intv cc uvlo falling l 4.1 4.3 v intv cc ovlo rising l 16.5 17.5 v intv cc ovlo falling l 14 15 v intv cc current limit intv cc > i intvcc_uvlo_rising (= 4.6v) l 38 48 58 ma intv cc < i intvcc_uvlo_falling (= 4.3v) 20 ma intv cc dropout voltage v in = 6v, i intvcc = 10ma, not switching 400 mv cg and fg gate drivers driver output rise time c cg = c fg = 3.3nf, intv cc = 8v (note 4) 25 ns driver output fall time c cg = c fg = 3.3nf, intv cc = 8v (note 4) 25 ns driver output high voltage l v intvcc C 0.2 v driver output low voltage l 0.7 v pmode selection pmode trip voltage pmode ramp up hysteresis l 1 1.2 30 1.4 v mv pmode input current pmode = 18v l 60 90 a preactive mode (tie pmode to 0v) preactive mode operating frequency range l 100 300 khz csw high trip voltage csw ramp up l 1 1.2 1.4 v csw high input current csw = 150v (note 7) l 250 500 a csw low trip voltage csw ramp down l C250 C150 C50 mv fsw trip voltage l 1 1.2 1.4 v fsw high input current fsw = 150v (note 7) l 250 500 a cg falling edge to csw rising edge prediction delay csw = 150khz (note 10), fsw = 0v, csp = C500mv l 5 100 300 ns cg falling edge delay to fg rising edge csw = 150khz (note 10), fsw = 0v, csp = C500mv l 10 50 80 ns lt 8311 8311f
6 for more information www.linear.com/lt8311 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, v intvcc = 8v, pmode = 5v, c cg = c fg = 100pf, unless otherwise noted. (note 2) parameter conditions min typ max units sync mode ( tie pmode to intv cc ) sync high trip voltage sync ramp up hysteresis l 0.9 1.2 C2.4 1.5 v v sync low trip voltage sync ramp down hysteresis l C1.5 C1.2 2.4 C0.9 v v sync minimum pulse width sync = 0v to 2v pulse sync = 0v to 6v pulse (note 5) l 40 20 100 ns ns sync input current C3.5v < sync < 3.5v sync = 10v (note 6, 7) l 300 1 400 a a sync propagation delay to cg/fg outputs sync rising edge (0v to 2v) to cg rising edge (note 8) sync rising edge (0v to 6v) to cg rising edge (notes 5, 8) sync falling edge (0v to 2v) to fg rising edge (note 8) sync falling edge (0v to 6v) to fg rising edge (notes 5, 8), c cg = c fg = 3.3nf l l 100 75 100 85 150 150 ns ns ns ns timer timeout frequency r timer = 41.2k r timer = 71.5k r timer = 221k l l l 425 255 80 505 300 100 585 345 120 khz khz khz timer short-circuit current timer = 0v l 40 60 a current comparator current comparator trip threshold csp ramp up, r csp = r csn = 0 l 48 62 72 mv csp ramp up, r csp = r csn = 1.62k (note 5) 0 mv current comparator blank time in preactive mode from rising cg edge until blanking ends (note 5) 250 ns current comparator blank time in sync mode from rising cg edge until blanking ends 400 ns csp current at low csp voltage csp = 0v (note 6) l 30 38 50 a csp current at high csp voltage csp = 150v (note 7) l 200 500 a csn current csn = 0v (note 6) l 0.1 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8311 is tested under pulsed load conditions such that t j ~ t a . the lt8311e is guaranteed to meet specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature are assured by design, characterization and correlation with statistical process controls. the lt8311i is guaranteed over the C40c to 125c operating junction temperature range. the lt8311h is guaranteed over the C40c to 150c operating junction temperature range, and the lt8311mp is guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note 3: the lt8311 includes overtemperature protection that is intended to protect the device during momentar y overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature is active. continuous operating above the specified maximum operating junction temperature may impair device reliability. note 4: rise and fall times of are measured between 10% and 90% points of a signal edge. note 5: guaranteed by design and/or correlation to static test. note 6: current flows out of pin. note 7: current flows into pin. note 8: propagation delay is measured between 50% point of the two signal edges of interest. note 9: ss charge current refers to current flowing out of ss pin after certain conditions satisfied upon lt8311 wake-up (see the flowchart for opto-control operation at start-up in figure 9). note 10: csw is a square waveform (duty cycle = 50%) with v high = 7v and v low = C0.7v. lt 8311 8311f
7 for more information www.linear.com/lt8311 typical performance characteristics preactive scheme waveforms (active clamp reset, ccm) preactive scheme waveforms (active clamp reset, light dcm) preactive scheme waveforms (active clamp reset, deep dcm) maximum csw duty cycle derating curve vs csw switching frequency and junction temperature feedback reference voltage feedback reference voltage vs v in delay from cg turn-off to csw rising edge vs csw switching frequency and junction temp jitter in cg turn-off delay to csw rising edge vs csw switching frequency and junction temp delay from cg turn-off to fg turn-on t a = 25c, unless otherwise noted. i l 5a/div csw 5a/div cg 10v/div fg 10v/div 8311 g04 2s/div i l 5a/div csw 5a/div cg 10v/div fg 10v/div 8311 g05 2s/div i l 5a/div csw 5a/div cg 10v/div fg 10v/div 8311 g06 2s/div temperature (c) delay cg falling to csw rising (ns) 150 175 125 100 25 0 75 200 50 8311 g01 100khz pmode = 0v intv cc = 8v ?75 ?25 25 75 ?50 0 125 150 50 100 300khz 150khz temperature (c) jitter (ns) 20 25 15 10 0 5 30 8311 g02 100khz pmode = 0v intv cc = 8v 300khz 150khz ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) delay cg falling to fg rising (ns) 60 50 30 40 70 8311 g03 pmode = 0v intv cc = 8v ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) maximum csw duty cycle (%) 80 85 75 70 55 50 65 90 60 8311 g07 100khz, 200khz pmode = 0v ?75 ?25 25 75 ?50 0 125 150 50 100 300khz 400khz temperature (c) fb voltage (v) 1.2290 1.2325 1.2255 1.2220 1.2150 1.2185 1.2360 8311 g08 ?75 ?25 25 75 ?50 0 125 150 50 100 v in (v) fb voltage (v) 1.2290 1.2325 1.2255 1.2220 1.2150 1.2185 1.2360 8311 g09 3 9 15 21 6 12 27 30 18 24 lt 8311 8311f
8 for more information www.linear.com/lt8311 typical performance characteristics ss charge current ss pull-down amplifier offset voltage opto-driver output swing low opto-driver output swing high opto-driver output swing high vs line voltage feedback input bias current v in quiescent current, no switching power good window t a = 25c, unless otherwise noted. temperature (c) fb input bias current (na) 133 115 80 98 150 8311 g10 ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) v in quiescent current (ma) 5.0 4.5 3.5 4.0 5.5 8311 g11 ?75 ?25 25 75 ?50 0 125 150 50 100 fb voltage (v) pgood voltage (v) 12 8 0 4 16 8311 g12 pgood = 100k to 12v 1.00 1.10 1.20 1.40 1.30 temperature (c) ss charge current (a) 10.5 10.0 9.0 9.5 11.0 8311 g13 ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) ss pull-down amp offset voltage (mv) 125 100 50 75 150 8311 g14 ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) opto low voltage (mv) 750 500 0 250 1000 8311 g15 ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) opto high voltage (v) 6.5 6.0 5.0 5.5 7.0 8311 g16 ?75 ?25 25 75 ?50 0 125 150 50 100 v in (v) opto high voltage (v) 6 7 5 4 2 3 8311 g17 3 9 15 21 6 12 27 30 18 24 lt 8311 8311f
9 for more information www.linear.com/lt8311 opto-driver short-circuit current typical performance characteristics intv cc ovlo intv cc current limit and short-circuit current cg/fg rise/fall time cg/fg rise/fall time vs intv cc voltage csw/fsw maximum input current opto-driver sink current intv cc regulation voltage intv cc uvlo t a = 25c, unless otherwise noted. temperature (c) opto current (ma) 15 5 10 20 8311 g18 ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) opto current (a) 350 300 250 200 400 8311 g19 ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) intv cc voltage (v) 7 8 6 5 3 4 8311 g20 ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) intv cc voltage (v) 4.6 4.8 4.4 4.2 4.0 8311 g21 uvlo + uvlo ? ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) intv cc voltage (v) 16.0 16.5 15.5 15.0 14.5 8311 g22 ovlo + ovlo ? ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) intv cc current (ma) 50 60 40 30 10 20 8311 g23 intv cc current limit intv cc short-circuit current ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) rise/fall time (ns) 30 25 20 10 15 8311 g24 fg fall time fg rise time cg fall time cg rise time ?75 ?25 25 75 ?50 0 125 150 50 100 intv cc 7v (not overdriven) intv cc (v) rise/fall time (ns) 25.0 22.5 20.0 15.0 17.5 8311 g25 fg fall time fg rise time cg fall time cg rise time 6 10 14 8 12 16 temperature (c) csw/fsw maximum input current (a) 250 240 220 230 260 8311 g26 v csw = v fsw = 150v ?75 ?25 25 75 ?50 0 125 150 50 100 lt 8311 8311f
10 for more information www.linear.com/lt8311 t a = 25c, unless otherwise noted. typical performance characteristics csp trip voltage vs series csp resistor (r csp ) sync high/low trip voltage prop delay from sync input to cg/fg outputs timer frequency csp maximum input current temperature (c) csw/fsw maximum input current (a) 190 180 160 170 200 8311 g27 v csp = 150v ?75 ?25 25 75 ?50 0 125 150 50 100 temperature (c) sync voltage (v) 1.0 1.5 0.5 0 ?1.5 ?2.0 ?0.5 2.0 ?1.0 8311 g28 sync high ?75 ?25 25 75 ?50 0 125 150 50 100 sync low temperature (c) propagation delay (ns) 140 160 120 100 70 60 90 180 130 150 110 170 80 8311 g29 ?75 ?25 25 75 ?50 0 125 150 50 100 cg rise/fg fall, sync = 2v cg rise/fg fall, sync = 6v cg rise/fg fall, sync = 10v fg rise/cg fall, sync = 2v fg rise/cg fall, sync = 6v fg rise/cg fall, sync = 10v temperature (c) frequency (khz) 400 500 300 200 0 100 600 8311 g30 r timer = 41.2k r timer = 221k r timer = 71.5k ?75 ?25 25 75 ?50 0 125 150 50 100 r csp (k) csp trip voltage (mv) 60 80 40 20 ?20 0 8311 g31 0.1 0.7 1.6 0.4 1.0 1.3 1.9 lt 8311 8311f
11 for more information www.linear.com/lt8311 pin functions csw (pin 1): catch mosfet drain sense pin. connect this pin to the external n-channel catch mosfets drain through a 2 k resistor ( typical) in preactive mode. mini- mize parasitic capacitance on the pin. connect to gnd in sync mode. fsw (pin 3): forward mosfet drain sense pin. con- nect this pin to the external n-channel forward mosfets drain through 2 k resistor ( typical) in preactive mode. minimize parasitic capacitance on the pin. connect to gnd in sync mode. fg (pin 5): forward mosfet gate driver pin. this pin drives the gate of the external n-channel forward mosfet. minimize trace length between this pin and the forward mosfet gate. intv cc (pin 6): internal linear regulators output pin. intv cc powers the gate drivers on the lt8311. the volt- age on this pin is internally regulated to 7 v. alternatively, the pin can be overdriven externally. a minimum of 4.7f (ceramic capacitor) must be placed from this pin to gnd. v in (pin 7): input supply pin. this pin must be locally bypassed. pmode (pin 8): preactive mode select pin. tying pmode to gnd enables preactive mode. tying pmode to intv cc enables sync mode. opto (pin 9): opto driver output pin. ti e this pin, through a series resistor, to the input of the opto-coupler. this pin can source up to 10 ma, sink 300 a typically, and is short-circuit protected. comp (pin 10): error amplifier output pin. tie an ex - ternal compensation network to this pin when using the lt8311s transconductance error amplifier as part of a voltage feedback loop. fb (pin 11): feedback pin. this is the inverting input of the lt8311s internal error amplifier. the fb pin voltage tracks the lower of the internal 1.227v reference and the ss pin voltage . 75na ( bias current) typically flows out of the pin. tie this pin to a resistor divider network from the output to set the desired output voltage. timer (pin 12): switching period timeout pin. a resistor from this pin to ground sets an upper limit on the sum of the forward and catch mosfet on times (including dead time between the two mosfets on period), every cycle. if the sum of the on times of the catch and forward mosfet, per cycle ( including the dead time), exceeds the timeout period programmed by the timer resistor, then all synchronous conduction will be shut down. synchro - nous conduction resumes when the timeout period is reset again. see the applications information section for more details on programming the timer resistor. keep the ground return trace of this pin short, and away from paths with switching noise. pgood (pin 13): output power good pin. the open-drain output will be pulled to ground when the fb pin voltage stays within 7% of the internal 1.227 v reference for a period of 175 s. the internal pgood comparator has a hysteresis of 3%. therefore, when fb exists outside 10% of the 1.227 v reference, the pgood pin will be pulled high by an external pull-up resistor or current source. ss (pin 14): soft-start pin. a capacitor from the ss pin to gnd will be charged up by sss internally trimmed 10 a current source. since fb tracks the lower of the ss pin voltage and the internal reference of 1.227 v, the charge rate of the ss pin can be used to set the slew rate at which the fb pin charges up to its regulation voltage of 1.227v. the ss pin typically charges up to 2 v. when using the lt8311 as part of voltage feedback loop, place a ceramic capacitor of at least 1 nf on this pin to gnd. for details on ss start-up and overshoot control functions, please refer to the applications information section. sync (pin 15): synchronization pin. the sync pin, used only in sync mode, serves as an edge-sensitive input to receive timing information for synchronous switching. it is typically driven with pwm synchronization signals from the primary-side ic through a pulse transformer. a nega - tive voltage slew on the sync pin (C1.2 v threshold) turns on the forward mosfet and turns off the catch mosfet. equivalently, a positive voltage slew (1.2 v threshold) turns on the catch mosfet and turns off the forward mosfet. tie the sync pin to gnd in preactive mode. cg ( pin 16): catch mosfet gate driver pin. this pin drives the gate of the external n- channel catch mosfet. minimize trace length between this pin and the catch mosfet gate. csn, csp (pin 18, pin 20): current sense differential inputs. csp and csn are the positive and negative inputs, respectively, of the lt8311s internal current sense com - parator. the pins are typically connected across the catch lt 8311 8311f
12 for more information www.linear.com/lt8311 block diagram mosfet to perform v ds current sensing. alternatively, if a more precise current sensing mechanism is desired, the pins may be connected across a sense resistor at the catch mosfets source. the current comparator trips at 62mv typical. the csp pin sources 38 a current, allowing trip voltages less than 62 mv to be set by placing a resistor in series with the csp pin. it is recommended to place an identical resistor in series with the csn pin to match any voltage offsets created by the input bias current (100na) of the current comparator. in preactive mode, the csp and csn pins must be configured to trip at zero or positive values of source to drain current in the catch mosfet (current in catch mosfet cannot be allowed to flow from drain to source in preactive mode). gnd ( exposed pad pin 21): ground. exposed pad must be soldered directly to local ground plane. pin functions 8311 bd intv cc intv cc v in v in uvlo c rst comp 1.227v v in 1v 10a 1.2v opto 1.227v r csw ss downamp synchronous controller 0.9v ?? r e n s n p to primary- side circuits m fg v in(sys) primary side secondary side primary ic m cg ? + 1.2v 1.2v 1.31v 1.14v + ? + ? + ? ? + + + ? + ? + ? + ? + ? ? + switching timeout oscillator uvlo + 1.227 reference uvlo/ ovlo + ? + ? 10 ss 14 c ss 140k r d 2k 100mv 62mv 38a 300k r csn r csp r fsw m1 9 pmode 8 csn 18 cg 16 csp 20 fg 5 fsw 3 csw 1 20k 6 intv cc c int vcc 7 v in 12 timer 15 sync 7v 11 fb 13 pgood 21 gnd r timer r pgood r fb1 c vin c out v out c pl v in 5.7v 5.7v r fb2 c c r c c f 20k l out a2 s1 a1 synchronous mode select 600mv + ? + ? lt 8311 8311f
13 for more information www.linear.com/lt8311 operation the lt8311 controls the synchronous mosfets and opto - coupler on the secondary side of a forward converter. synchronous control of low r ds( on) mosfets can typically lead to lower power dissipation in forward converters. the lower power dissipation can improve converter efficiency, resulting in long term cost savings by lowering input power requirements to support a certain level of output power. improved efficiency can also reduce the size of heat sinks required to dissipate the heat generated in the rectifiers; consequently increasing the operating ambient temperature range which may be useful in many industrial applications. the lt8311 also offers opto-coupler control for accurate output voltage regulation over line and load. the lt8311s opto- coupler control circuitry comes with a host of start- up and steady-state functions to ensure robust transient re - sponse during power - on and output short- circuit recovery . fundamentals of forward converter operation in ccm the timing diagram of a forward converter operating in continuous conduction mode ( ccm) is shown in figure 2. the timing diagram is broken into six regions of operation. please refer to figures 1 and 2 for the following explana- tion of each region of operation. region 1 (figure 2) when out goes high, m1 turns on. cg should already be at 0 v before out goes high, to ensure that m cg does not cross conduct with m1. the lt8311s preactive mode, which will be explained later, is an innovative scheme to turn off m cg before m1 turns on. fg must be high during this period to keep the forward mosfet, m fg on, thereby conducting the output inductor current, i lout , ( via the transformers secondary winding) through a low imped- ance path . during this phase, magnetizing current, i lmag , builds up in the transformers magnetic core, and flows from v in to gnd through m1. output inductor current, i lout , ramps up at a rate of (v csw C v out ) / l out . region 2 (figure 2) when out goes low, and turns off m1, the transformer becomes high impedance, and stops conducting i lout . since current in the output inductor cannot go to zero instantaneously, it pulls the drain of the catch mosfet, csw, towards ground. ultimately csw gets clamped at a diode voltage below ground by m cg s body diode which now sources the output inductor current ( similar to a catch diode in a traditional buck converter). csw collapsing equivalently causes the transformers secondary winding voltage to become smaller. through transformer action, figure 1. forward converter with active clamp reset (in red) or resonant reset (in blue) 8311 f01 v in v drain_m2 ?? n s n p primary ic out v out c out l out i lout csw secondary ic fsw swp i lmag l mag m fg m1 r load m cg v cl c cl aout m2 c aout c rst d2 fg cg active clamp reset (red) resonant reset (blue) + ? lt 8311 8311f
14 for more information www.linear.com/lt8311 operation figure 2. active clamp forward converter timing diagram in ccm. resonant reset waveforms in blue d ? t per t per aout v gate m2 (m2 source = 0v) out (m1 source = 0v) swp i lmag csw cg 0.7 (clamped by d2) 0.7 (clamped by d2) m2 off m2 off m2 on m2 on m1 on 0.7v v in m1 on m1 off 0v 0v 0v 0v time 0v 0v 0v 0a 0v 0v 0v 0v 0v 0v 0v m cg off m cg on m cg off m cg on m fg on m fg off m fg on m fg off m1 off fsw fg i lout active clamp pmos control signal active clamp pmos gate primary nmos switch gate primary-side waveforms secondary-side waveforms primary nmos switch drain transformer magnetizing inductance current catch fet drain catch fet gate forward fet drain forward fet gate output inductor current regions of operation 0.7v 0.7v 8311 f02 di dt = v in l mag di d t = ? 1 l mag ? v in ? d 1 ? d v in ? d ? t per l mag v out ? t per 2 ? l mag ? c rst di d t = v csw ? v out l out di d t = ?v out l out v out r load v out ? (1 ? d) ? t per l out v in ? n s n p v out 1 ? d v in 1 ? d 2 3 1 4 6 5 l mag ? c rst t res = v in ( 1 + d ? t per ) 2 l mag ? c rst lt 8311 8311f
15 for more information www.linear.com/lt8311 operation figure 3. with fg on, i lmag is conducted through m fg to ground on the secondary side when m1 turns off figure 4. detail of region 3 from the timing diagram in figure 2. when m fg turns off in active clamp reset, i lmag initially slews up swps voltage from v in to v cl + 0.7v, at which point m2s body diode turns on and allows i lmag to flow into c cl the primary winding voltage gets smaller too, effectively moving swp towards v in . since m fg is still on, and m cg s body diode is on, the secondary winding voltage gets clamped at about a diode voltage. through transformer action, swp gets clamped to approximately v in . i lmag flows in the secondary windings, as shown in figure 3, flowing from the drain to source of m fg , to ground. m cg s body diode sources i lout and i lmag . region 3 (figure 2) when fg goes low, it allows transformer reset action to begin. i lmag no longer has a low impedance path through m fg on the secondary side. as a result, it jumps back to the primary side, flowing into the primary-side resonant capacitor. in resonant reset, i lmag flows into c rst as soon as m fg turns off, causing swps voltage to rise up quasi- sinusoidally, with a time constant set by l mag and c rst . in active clamp reset, when m fg turns off, i lmag intially slews up swps voltage quickly. as shown in figure 2, i lmag does not flow into the active clamp capacitor as soon as m fg turns off. the voltage across c cl (= v cl = v in /(1-d)) initially reverse biases m2s body diode. only when swps voltage gets high enough to forward bias m2s body diode, does i lmag begin to flow into c cl . the voltage where this happens is when swp = v cl + 0.7 v. at this point, swps voltage rises up at a rate determined by the time constant of l mag and the active clamp capacitor, which is typically much larger than the resonant reset capacitor. v drain_m2 swp m2 body diode off m2 body diode on m2 on m fg turns off v cl = v in 1 ? d t rise proportional to l mag and c cl v cl + 0.7v v cl v in 0.7v 0v v in ? v cl time 8311 f04 8311 f03 v in ? ? n s n p m1 off l out i lout i lmag l mag m fg m cg fg on cg off i lmag lt 8311 8311f
16 for more information www.linear.com/lt8311 the ultimate goal of both reset mechanisms is to raise the swp node to a voltage higher than v in , imposing appropriate volt seconds on l mag , and allowing the magnetizing current to reset. resetting the magnetic core every cycle prevents magnetic flux buildup within the core, and thereby prevents transformer saturation. fsw tracks the swp node during transformer reset. cg going high, allows i lout to switch over from being conducted by m cg s body diode to m cg itself. region 4 (figure 2) 1. active clamp reset case (red waveform): aout going low causes the gate of m2 to be driven below ground by the decoupling capacitor, c aout . this causes m2, the active clamp pmos, to turn on. m2 must be turned on before i lmag becomes negative, to allow i lmag to sustain conduction through the active clamp capacitor and get fully reset. active clamp reset completes by the end of region 4, and i lmag is reset to a negative value. 2. resonant reset case ( blue waveform): resonant reset ultimately completes when swps quasi-sinusoidal waveform returns to v in , by which point i lmag is reset to a negative value. fsw is eventually clamped by m fg s body diode, and conducts i lmag , through the second- ary windings , towards the output inductor ( similar to figure 3, but with i lmag direction reversed on primary and secondary sides). with a diode voltage imposed across the secondary windings, transformer action causes the primary winding to have a similar voltage (scaled by turns ratio), resulting in swps voltage getting clamped to v in . m cg continues conducting i lout C i lmag . region 5 (figure 2) active clamp reset case: aout goes high, turning off m2. i lmag , being negative, causes the voltage on swp (m1s drain) to get pulled towards v in , resulting in the transformers primary winding voltage becoming smaller. by transformer action, the secondary winding voltage also becomes smaller. with m cg on ( holding csw at 0 v), and the transformer secondary winding voltage becoming smaller, fsw collapses towards 0v. region 6 (figure 2) eventually, in similar fashion to the resonant reset case, fsw is clamped to a diode voltage below gnd by m fg s body diode, which now conducts i lmag through the secondary windings, towards the output inductor. with m fg s body diode on, and m cg on, the secondary winding voltage gets clamped to about a diode voltage. through transformer action, swp gets clamped to approximately v in . cg goes low, turning off m cg before m1 can turn on. i lout C i lmag is conducted through m cg s body diode. fg goes high, turning on m fg . eventually, when m 1 turns on, i lout will be conducted through the transformers secondary winding, and will flow from the source to drain of m fg . operation lt 8311 8311f
17 for more information www.linear.com/lt8311 lt8311 synchronous control schemes the lt8311 offers two modes of synchronous control: 1. preactive mode: no pulse transformer needed; dcm operation at light load. enabled by tying the pmode pin to 0v. use a schottky diode across m cg (figure 20). 2. sync mode: pulse transformer needed; fcm or dcm operation at light load. enabled by tying the pmode pin to intv cc . preactive mode synchronous control m cg turn-on/off timings in preactive mode "preactive" is short for "predictive" + " reactive". in preactive mode, the lt8311 controls the secondary synchronous mosfets without any communication from the primary- side ic. in preactive mode, the catch mosfet, m cg , is turned on ( cg rising edge in figure 5) when the voltage on its drain, csw, is detected to be below C150 mv, and the forward mosfet, m fg , is detected to be off. m cg is turned off when the first of two events after m cg s turn- on occurs: ? predictive m cg turn-off (figure 5): in predictive turn- off, the lt8311 predicts when m1 will turn on in the next cycle, and turns off m cg 100 ns prior to this event. predictive turn-off of m cg prevents cross conduction between m cg and m1. m1s turn-on timings are pre- dicted by phase locking to the rising edge of present and past csw cycles. predictive turn-off relies on the periodicity of m1s turn-on edge, an inherent aspect of fixed-frequency operation. furthermore, the predictive turn-off is designed to be independent of the duty cycle of the system, which allows m cg to be correctly turned off, even during load/line transients. predictive turn-off will typically be the dominant turn-off mechanism for m cg in ccm. ? reactive m cg turn-off ( figure 6): reactive turn-off forces the forward converter to operate in dcm at light load. in reactive turn-off, the lt8311 turns off m cg when the current in m cg (i mcg ) trips the lt8311s internal current comparator. the inputs to this current comparator are the csp and csn pins. typically, the csp and csn pins will be configured to trip at almost zero current in m cg , which should correspond to nearly zero current in the output inductor. reactive turn-off will typically be the dominant turn-off mechanism for m cg in dcm. the lt8311s seamless transition between predictive and reactive portions of preactive mode allows the catch mosfet to be turned off at the correct time to avoid cross conduction or avalanching. m fg turn-on/off in preactive mode in preactive mode, m fg is turned on after m cg s turn-off edge is detected, and the voltage on the drain of the forward mosfet, fsw, is detected to be below 1.2 v. waiting for fsw to fall below 1.2 v ensures that transformer reset is close to completion. m fg is turned off when the voltage on csw is detected to be below C150mv. since preactive mode requires each mosfet to be turned on only after the other mosfets turn-off edge is detected, the system requires a start point where one of the two mosfets begins switching. preactive modes start point happens by turning on m cg first to commence switching. preactive mode shutdown and start-up preactive mode is designed with many features to facilitate smooth start-up of synchronous control and shut down of the scheme when necessary. prior to starting switching activity, the lt8311 evaluates conditions on the forward converters secondary side to determine if switching can commence. the evaluation period ends when four specific conditions, are satisfied for a period of three continuous csw switching cycles ( rising edge to rising edge). if any of the conditions are violated, the evaluation period is reset, and switching activity is kept shut off. during this evaluation period, the secondary side current will flow through the body diodes of m cg and m fg . the four conditions are: 1. v in must be greater than its uvlo voltage 2. intv cc must be within its uvlo/ovlo limits 3. the timer pin should not have timed out. this feature exists to ensure that the lt8311 ceases switching in the event that the primary side stops switching. operation lt 8311 8311f
18 for more information www.linear.com/lt8311 figure 5. during the predictive portion of preactive mode, the lt8311 phase locks into the csw rising edge and turns off m cg 75ns prior to this edge figure 6. during the reactive portion of preactive mode, the lt8311 turns off m cg when the current in m cg , i mcg , trips the lt8311s internal current comparator. the inputs to the comparator are csp and csn and the current sense trip voltage is programmed by choosing appropriate csp/csn series resistors 0v 0v 0v primary-side ic controls timing of out signal lt8311 uses i mcg information to determine fg/cg control timings during the reactive portion of preactive mode waveforms in dcm when csp-csn trips internal current comparator m cg turns off 8311 f06 out i mcg csw cg time 0a 0a i lout m1 turn-on edge m1 turn-on edge 0v 0v 0v 75ns predictive delay primary-side ic controls timing of out signal lt8311 uses csw/fsw information to determine fg/cg control timings during the predictive portion of preactive mode waveforms in ccm 8311 f05 out m1 turn-on edge csw cg time m1 turn-on edge m cg turn-off edge m cg turn-off edge reset mechanism primary ic out v in v out c out ?? lt8311 fsw csw csp cg csn l out i lout fg csw fsw i mcg n s n p m cg m1 m fg operation lt 8311 8311f
19 for more information www.linear.com/lt8311 4. the csp and csn pins must not trip the internal current comparator within a 150 ns period of time called " current sample window." this function helps the lt8311 detect very light load conditions, dur - ing which time it will keep synchronous conduc - tion shut off, thereby improving system efficiency. how the current sample window works: the current sample window exists regardless of whether m cg is turned on or not, in any given cycle. when csw is detected to fall below C150 mv, the lt8311 starts a blank time of 200 ns. upon completion of this blank time, the lt8311 starts a 150ns current sample window. if the csp/ csn pin inputs cause the internal current compara - tor to trip during this 150 ns window, the lt8311 will interpret this as a condition of very light load, at which point it will stop synchronous conduction and start the evaluation period again. please see "configuring csp/ csn inputs of current sense comparator in preactive mode in the applications information section. when all four conditions are valid for three continuous csw cycles, the evaluation period ends and the lt8311 gets ready to start switching. switching commences with the lt8311 turning on m cg for its minimum on-time. if any of the four conditions listed are violated at any point during switching activity, the lt8311 will shut down all synchronous conduction and restart the evaluation period. during preactive mode start- up, the lt8311 internally soft- starts the on-time of m cg , allowing the forward converter to gradually transition from full cycles of nonsynchronous m cg conduction ( secondary-side current flowing through body diode of m cg ) to full cycles of synchronous m cg conduction. sync mode synchronous control sync mode allows the lt8311 to operate in forced con - tinuous mode ( fcm) at light loads. in sync mode, a pulse transformer ( see t2 in figure 7) is required to allow the lt8311 to receive synchronization control signals from the primary-side ic. these control signals are interpreted digitally ( high or low) by the lt8311 to turn on/off the catch and forward mosfets. fcm operation allows the forward converter to avoid operation in discontinuous conduction mode ( dcm) at light loads, by letting the inductor current go negative. hence, even at zero load, the inductor current remains continuous and the converter runs at a fixed frequency. m cg turn-on/off timings in sync mode in sync mode, m cg turns on when the signal on the sync pin is higher than 1.2 v. m cg turns off when the signal on the sync pin is lower than C1.2v. m fg turn-on/off timings in sync mode in sync mode, m fg turns on when the signal on the sync pin is lower than C1.2 v. m fg turns off when the signal on the sync pin is higher than 1.2v. the r sync and c sync time constant must be appropriately chosen to generate a sufficient pulse width at a particular overdrive voltage (see " picking pulse transformer and high pass filter" in the applications information section). typical values for c sync and r sync are 220 pf and 560, respectively. operation lt 8311 8311f
20 for more information www.linear.com/lt8311 figure 7. in sync mode, the primary side ic sends s out signals through a pulse transformer to the lt8311s sync pin. sync < 1.2v turns on m fg and turns off m cg . sync > 1.2v turns on m cg and turns off m fg 0v 0v 0v 0v 0v 0v 0v 0v 0v 0v 0v 0v 0v 0v 1.2v ?1.2v primary-side ic controls timing of out and s out signals lt8311 controls fg and cg timing based on sync input signal in sync mode 8311 f07 out s out sync cg fg time reset primary ic s out out v in v out c out ?? lt8311 cspcgcsn l out fg sync t1 ?? t2 i mcg n s n p r sync c sync m1 turn-on edge m1 turn-on edge m fg turn-on edge m fg turn-on edge m cg turn-on edge m cg turn-on edge m cg m1 m fg sync mode shutdown in sync mode, the lt8311 will shut off both secondary- side mosfets, m cg and m fg , if any of the following conditions are true: 1. v in is less than its uvlo voltage 2. intv cc outside its uvlo/ovlo limits 3. the timer pin has timed out ( see the applications information section for details on programming the timer pin resistor). 4. the csp and csn pins have tripped the lt8311s in - ternal current comparator during m cg s on-time. the current in m cg , i mcg , is sensed after a 400 ns blank time has expired. this blank time starts at the turn-on edge of m cg . see the applications information section for details on configuring the csp and csn pins in sync mode. operation lt 8311 8311f
21 for more information www.linear.com/lt8311 opto-coupler control the lt8311 offers opto-coupler control to allow output voltage feedback from the secondary to the primary side in a forward converter. used in conjunction with a primary- side ic, the entire system offers fixed frequency peak current mode control that has excellent line/load regulation and quick transient response. a basic understanding of the lt8311 s opto- coupler control scheme can be obtained by referring to figure 8. the lt8311 senses the output voltage through a resistor divider (r fb1 and r fb2 ) connected to its fb pin. the fb pin voltage is compared to the lower of two inputs: ? an internal voltage reference of 1.227v ? soft-start (ss) pin at start-up, the ss pin capacitor, c ss , is charged up by the lt8311s internally trimmed 10 a current source. since fb tracks the lower of the ss pin and the 1.227 v refer - ence, the fb pin ( and by extension the output voltage) is for ced to soft-start at the slew rate set by the capacitor, c ss , connected to the ss pin. note: to ensure that the soft-start time of the converter is controlled by the lt8311s ss capacitor, c ss , it is important to program the primary ics soft-start faster, to get out of the way. if this is not done, the converters soft-start time will be dominated by the primary ics soft start, and the lt8311 will simply adjust its ss pin voltage and slew rate to match the slower soft start time set by the primary-side ic. when the ss pin voltage gets higher than the 1.227 v refer - ence, the fb pin starts to track the 1.227 v reference. the output, therefore, regulates at a voltage set by the r fb1 / r fb2 divider network, and the fb pins regulation voltage of 1.227 v. the ss pin capacitor continues to get charged up by the 10 a current source until it reaches its internal clamp voltage of 2v. operation figure 8. the lt8311 provides voltage feedback, as part of a peak current mode control system, in a forward converter v in v out c out cg fg ?? l out n s n p + ? v c is also referred to as comp in some primary-side ics v ref v c + ? r2 r1 a3 a4 lt8311 opto control 1v + ? 140k 20k a2 comp 1.227v 10a 1.227v + + ? 2k 0.9v fb ss r fb1 c pl r fb2 c c r c r load c f a1 c ss r sns r d gain opto 8311 f08 11 14 10 9 + ? m cg m1 m fg r e lt 8311 8311f
22 for more information www.linear.com/lt8311 with ss charged up to 2 v, the transconductance error amplifier, a1, sinks or sources current from its output, comp, if there is any voltage difference between the fb pin voltage and the 1.227 v reference. the comp pin, offset by 0.9 v, serves as the input to the opto-driver, a2. if an increase in output load current causes the fb pin voltage to be lower than 1.227 v, a1 drives the comp pin high. comp going high forces a2 to drive opto low, sourcing less current through r d into the opto-coupler. since an opto-couplers output current is directly propor- tional to its input current, this decreased input current for the opto- coupler will cause its output current, and therefore its emitter voltage at r e , to decrease as well. the drop in r e voltage causes a3, through its inverting action, to drive its output, v c , higher. an increase in the v c voltage causes the comparator, a4, to command a higher sense voltage across the r sns resistor, commanding m1 to run at a higher peak current. since the current through m1 is figure 9. flowchart for lt8311 opto control operation at start-up comp < 2.2v no ss pull-down amplifier enabled opto-driver activation 8311 f09 1. error amp disabled: comp pin voltage charged up to comp hi clamp = 2.2v; t rise 1.1 ? 10k ? c c 2. ss pull-down amplifier disabled 3. ss pull-up amplifier activated. this amplifier only has sourcing capability (1ma slew current), and will drive ss pin voltage close to fb pin voltage (v fb ? v ss ? 16mv) 4. ss 10a charge current activated 5. opto-driver disabled: opto pin voltage held at 0v opto-driver deactivation v in > 3.7v 1. ss pull-up amplifier disabled 2. ss pull-down amplifier enabled: this amplifier only activated when fb pin voltage is less than 50% of fb reference voltage. this amplifier only has sinking capability (12ma slew current) and will drive ss pin voltage to be no higher than 90mv above fb 1. error amp enabled: error amp can now drive comp based on comparing fb voltage with ss voltage or 1.227v reference 2. opto-driver enabled: opto-driver can now drive opto pin as a function of comp pin voltage ss > fb ? 16mv yes yes no operation lt 8311 8311f
23 for more information www.linear.com/lt8311 directly proportional to the output inductor current ( m1 current ? n p /n s = i lout ), an increase in m1s peak current translates into an increase in the output inductors peak current. in essence, the feedback loop is commanding the output inductor peak current to meet the demands of the increased load current, with the ultimate goal of helping the output voltage recover from a load step and stay regulated. opto-control operation at start-up for applications connecting the lt8311s v in pin directly to the converter output, the lt8311 includes intelligent circuitry to ensure no interruption in the switching of the primary-side mosfet upon the lt8311s turn-on. the lt8311 turns on when its v in pin ( and therefore the converter output voltage when v in is directly connected to the output) exceeds 3.7 v. without intelligent circuitry, this v out level will cause the fb pin voltage of the lt8311 to be greater than the voltage on the lt8311s ss pin (which is typically at 0 v upon turn-on of the ic), causing ampli - fier a1 to drive the comp pin low. this drives the opto pin high, which causes full current into the opto-coupler and terminates switching of the primary-side mosfet. termination of the primary-side mosfets switching can lead to the converters output voltage dropping, which could cause the lt8311 to lose power and shut off. the lt8311s intelligent circuitry prevents this situation using two unique features. it has a built-in 100 mv hysteresis on figure 10. opto control operation at start-up figure 11. power good activates (pgood = low) when the lt8311 s fb pin voltage is within 7% of its regulated target (1.227v). the pgood pin is pulled up externally to a 12v housekeeping supply through a 100k external resistor its v in uvlo voltage, so that upon getting power, it can tolerate up to a 100 mv drop on its v in pin before losing power again. even more importantly, the lt8311 has an opto-control start-up system that keeps the lt8311s opto-control brains turned off until all relevant node voltages within the voltage loop are prebiased to a state where they will not cause switching activity to cease when the loop is eventually enabled. as shown in figure 9 and the scope shot in figure 10, the lt8311s opto-control operation at start -up involves slewing the ss pin voltage close to the fb pin voltage, slewing the comp pin voltage to its high clamp voltage, and keeping the opto pin voltage held low. during this phase, the inductor current ( and by extension, the output voltage) is controlled by the soft-start function provided by the primary- side ic. upon completion of the state machine, the lt8311 allows the feedback loop to be functional again, and the fb pin voltage tracks the lt8311s ss pin voltage until fb finally gets to its regulation target of 1.227v. power good the lt8311 offers output power good monitoring to assist with system level design. the lt8311s pgood pin is pulled low internally when the fb pin voltage stays within a 7% window of the 1.227 v reference for a period of 175 s. waiting for 175 s to elapse prevents the pgood pin from indicating false positives during transient events. operation comp 1v/div ss 200mv/div fb 200mv/div opto 500mv/div 8311 f10 5ms/div pgood 5v/div fb 500mv/div 8311 f11 2ms/div lt 8311 8311f
24 for more information www.linear.com/lt8311 operation the pgood comparator has 3% hysteresis. therefore, when the fb pin voltage is driven away from its regulated value of 1.227 v by 10%, the pgood pins internal pull- down shuts off immediately. as a result, the pin is pulled high by an external resistor or external current source connected to a supply voltage. the pgood pins output can be fed to a microcontroller that make decisions based on the state of the output voltage. output overshoot control helps with short-circuit recovery the lt8311 provides output overshoot control by activating its soft-start pull-down amplifier (ss downamp in the block diagram) any time the fb pin voltage is less than 50% of the fb reference voltage (1.227 v). this is particularly helpful with output voltage recovery after the removal of a short-circuit condition or after a heavy load transient. the ss pull-down amplifier will sink whatever current is necessary ( up to its maximum sink capability of 13 ma), to ensure that the ss pin voltage gets no higher than 100mv above the fb pin voltage. during output short- circuit events, when the fb pin voltage is pulled to ground, the ss pull- down amplifier gets activated and pulls the ss pin voltage to 100 mv above the fb pin voltage. eventually, when the short-circuit condition is over, the fb pin voltage gradually rises up with the ss pin at a slew rate set by c ss and the 10a charge current. this allows the output to recover gradually from the short-circuit condition. note that when the lt8311 has its v in pin powered directly from the output of the forward converter, it will lose all its brains during a short-circuit event. under this scenario, output overshoot control will not be in effect until the lt8311 gets brains again, until which point, the output inductor current and the output voltage will be controlled by the primary-side ics soft-start function. (a) output overshoot control with c ss = 1nf. lt8311 v in powered from a 12v housekeeping supply, which also pulls up on the pgood pin through a 100k external resistor (b) output overshoot control with c ss = 33nf. lt8311 v in powered from a 12v housekeeping supply, which also pulls up on the pgood pin through a 100k external resistor figure 12. output overshoot control at start-up pgood 10v/div ss 500mv/div fb 500mv/div 8311 f12a 1ms/div pgood 10v/div ss 500mv/div fb 500mv/div 8311 f12b 2ms/div lt 8311 8311f
25 for more information www.linear.com/lt8311 applications information v in bias supply the lt8311s v in pin can be powered in various ways. place at least a 2.2 f ceramic bypass capacitor close to the pin. picking an appropriate bias supply to power up the lt8311 requires consideration of the following criteria: 1. the v in pin, in certain configurations, may be the only supply to the lt8311s intv cc pin, which provides gate drive to the catch and forward mosfets. in such situations, v in s bias supply must be high enough to provide adequate gate-drive voltage (typically 5 v to 7v) for both synchronous mosfets. 2. v in s bias supply must be able to source: a. lt8311s v in current (4.5ma typical) b. intv cc gate-drive current when using v in to sup- ply the intv cc pin (typically 10ma to 30ma) c. opto-driver sour ce current (typically 1ma to 5ma) 3. v in start-up and short-circuit conditions: a. v in must come up in reasonable time to allow the lt8311 to begin synchronous and opto-coupler control. while synchronous control is shut off, the secondary-side current will flow through the body diodes of the secondary synchronous mosfets. while opto-control is off, the forward converter will operate open-loop, using a volt-second clamp to control v out if operating with lt3752, lt3752-1 or lt3753 on the primary side. b. v in may be shorted to gnd during transient events. for instance, v in powered from the output voltage, will be driven to 0 v during an output short-circuit. the forward converter must be able to ride through the momentary loss of power to the lt8311, which is often easily accomplished by appropriately configuring soft-start control on the primary-side ics. refer to the lt3752/lt8310 data sheets for details on configuring soft- start control on the primary-side ic. with the previous criteria in mind, there are three meth- ods (1-3), listed below , for powering up the lt8311. for preactive mode, use method 1, 2 or 3. for sync mode fcm, use method 1 or 3; for dcm, use method 1, 2 or 3. 1. power from the lt3752s housekeeping supply (see figure 21 in the typical application section). being a flyback converter rather than a ldo, the lt3752s housekeeping supply is an efficient supply source. it can be connected through an external winding to the lt8311s v in and intv cc pins, and can be set high enough to provide adequate gate drive for the catch and forward mosfets, but low enough to minimize efficiency and thermal losses. the housekeeping supply comes up as soon as the lt3752 receives input power, so power is delivered to the lt8311 without delay. 2. power directly from v out . at output voltages lower than 10 v, careful consideration must be given to the output voltage start-up time, ensuring that the lt8311 can turn on and provide synchronous/opto control well before the output voltage approaches regulation. it is also important to ensure, at these lower output voltages, that sufficient gate drive voltage can be provided to the external mosfets. at higher v out voltages, efficiency and thermal considerations related to the ics internal power dissipation can become important criteria. in addition, at higher v out voltages, it is important to ensure that voltage transients on the v in pin do not exceed the pins abs max rating of 30v. 3. use a buck circuit from an auxiliary transformer wind - ing, as shown in figure 13. this circuit has the benefit of being highly efficient, and is fairly simple to design. it is particularly useful for low output voltage applica- tions (3.3 v or 5 v) that do not have an external house- keeping supply , and where powering directly from the output voltage is inadequate. in this configuration, the buck circuits output voltage derives its energy from secondary - side switching pulses that also source energy to the forward converters main output voltage, v out . careful consideration must be given to ensure that the buck output voltage comes up well in time, and turns on the lt8311 to provide synchronous and opto control before the forward converters actual output voltage gets close to regulation. if there is a need to speed up lt 8311 8311f
26 for more information www.linear.com/lt8311 applications information the time taken by the buck converter output voltage to get to its target, relative to the forward converters main output voltage, often a simple technique is to slow down the main output voltage start-up time by increasing the soft-start capacitor on the primary-side ic. intv cc bias supply the intv cc pin powers the catch and forward mosfet gate drivers of the lt8311. tw o configurations exist for biasing up the intv cc pin, as shown in figure 14: 1. in the first configuration, the lt8311s on-chip ldo regulates the intv cc pin voltage from the v in supply. when the v in pin voltage is low, the internal ldo will operate in drop-out, driving the intv cc pin to about 400mv below the v in pin voltage. when the v in pin voltage is high, the internal ldo will regulate intv cc s voltage to 7 v. ensure that v in s supply voltage does not exceed v in s abs max voltage of 30 v. if intv cc drops below its uvlo voltage (4.6 v rising and 4.3 v falling), all synchronous switching will be stopped. the maximum guaranteed current that the intv cc ldo can source is figure 13. buck circuit generates v aux supply, which powers lt8311s v in and intv cc pins figure 14. v in and intv cc pin configurations 8311 f13 v in buck auxilliary supply ?? n s n p v out v aux lt8311 ? n aux v in intv cc v aux = v out ? n aux n s ? ? ? ? ? ? m cg m1 m fg 40ma. ensure that the total gate charge (q g ) current required by both secondary mosfets, m cg and m fg , is less than 40ma: i mosfet_total = f sw ? (q g_mcg + q g_mfg ) < 40ma where f sw is the converter s switching frequency, q g_ mcg is the gate charge ( q g ) rating of m cg and q g_ mfg is the gate charge (q g ) rating of m fg . this configuration, utilizing the lt8311s internal ldo, will suffice for most applications, limited only by thermal considerations related to the ldos power dissipation. keeping the power dissipation to a minimum will help lower the operating junction temperature of the lt8311 , potentially allowing the system to operate over a wider ambient temperature range: ldo power dissipation = (v in C intv cc ) ? i mosfet_ total lt8311 operating junction temperature v ja ? (v in ? 4.5ma + ldo power dissipation + v in ? i opto ) + t a where v ja is lt8311s junction-to-ambient thermal resistance and is typically 38 c/w; i opto is the current 8311 f14 intv cc v in v in < 30v regulated to 7v lt8311 ldo 4.7f intv cc v in v in < 16v lt8311 ldo 4.7f lt 8311 8311f
27 for more information www.linear.com/lt8311 applications information sourced into the opto-coupler by the lt8311s opto pin; 4.5 ma is the typical v in current of the lt8311; t a is the ambient temperature. 2. in the second configuration, the v in pins bias supply drives the intv cc pin through a direct connection, bypassing the internal ldo. this configuration re- duces power dissipation inside the ic by not having to incur any power loss within the intv cc ldo. use this optional configuration for v in voltages that are below 16v , allowing sufficient margin for intv cc to stay below its ovlo(+) voltage of 16.5 v. ensure that v in , during transients, does not exceed intv cc s abs max voltage of 18v. whe n an external supply or auxiliary winding is available , use this configuration ( tying v in and intv cc together) to deliver power to the ic. this configuration is most applicable when using the lt3752 as a primary-side ic. the lt3752s housekeeping supply can be connected to the lt8311s v in and intv cc through an auxiliary winding, as shown in figure 21 in the typical applica- tions section. int v cc should be bypassed with a minimum of 4.7f ceramic capacitor to ground for all three configurations. place the capacitor close to the intv cc pin, ensuring that the ground terminal of the capacitor has the shortest pos- sible return path to the lt8311s ground (exposed pad). lt 8311 op to control fundamentals setting output voltage figure 15 shows how to program the forward converters output voltage with a resistor divider feedback network. connect the top of r fb1 to v out , the tap point of r fb1 / r fb2 to the fb pin, and the bottom of r fb2 to ground. the ground return of r fb2 must be kept as close as possible to the ground of the lt8311, and must be kept away from the forward converters power path. the power path contains switching currents, and possibly large value currents (de - pending upon the load) which may introduce unintended noise, or i ? r drops into the fb resistor divider path. the fb pin regulates to 1.227 v and has a typical input pin bias current of 120na ? owing out of the pin. the output voltage is set by the formula: v out = 1.227 ? 1 + r fb1 r fb2 ? ? ? ? ? ? ? 120na ? r fb 1 figure 15. setting output voltage of forward converter 8311 f15 gnd fb lt8311 v out 120na r fb2 r fb1 lt 8311 8311f
28 for more information www.linear.com/lt8311 figure 16. forward converter voltage feedback loop with lt8311 on secondary side and lt3752 (or) lt8310 on primary side applications information v cc(opto) v in(lt8311) ? 1.7v < v cc(opto) < 6v g mea = 350umhos r outea = 4.5m max opto source current = 10ma max comp src current = 20a max comp sink current = 30a v in v out c out1 cg fg ?? l out c out2 i out n s n p + ? r e v x comp/v c voltage to command 0 r sns current 1.25v , 0.7v comp/v c voltage to command max r sns current 2v , 1.2v true voltage amp transconductance amp isensep (sense) fb (fbx) out (gate) v ref = 1.25v , 1.60v max c omp /v c src current ~ 11ma, 13a max comp /v c sink current 11ma, 12.5a r2 (typical) 33k, 150k v ref comp (v c ) + ? r1 lt8311 1v + ? 140k 20k comp 1.227v + ? 2k 0.9v fb r fb1 c pl r fb2 c c r c r load c f r sns r d r in(opto) = 1/g m(opto) lt3752 or lt8310 opto 8311 f16 i primary v isensep v comp_primary i opto_out c opto i f + ? curr_gain = 7.5v/ v , 5v/v r2 r1 = r2 / gain 1 < gain (typical) < 2 m f r esr m cg m1 m fg picking loop compensation components figure 16 shows a typical loop associated with a forward converter, using the lt8311 on the secondary side, and the lt3752 or lt8310 as the primary-side ics. parametric values specific to the lt3752 are shown in red, while those specific to the lt8310 are shown in blue. the forward con - verter loop shown is a peak current mode control system. the optimum values for loop compensation depend on the ic used on the primary side and the lt8311, as well as the operating conditions of the converter ( input voltage range, output voltage, load current, etc.). to compensate the voltage feedback loop around the lt8311, a series resistor/capacitor network is usually connected from the lt8311's comp pin to gnd. for most applications, the capacitor c c should be in the range of 4.7 nf to 47 nf, and the resistor r c should be in the range of 2 k to 20 k. if the r c value is too large, the part will be more susceptible to high frequency noise and jitter. if the r c value is too small, the transient performance will suffer. the value choice for c c is somewhat the inverse of the r c choice: if too small a c c value is used, the loop may be unstable and if too large a c c value is used, the transient performance may suffer. a small capacitor, c f , is often connected in parallel with the rc compensation network to attenuate the comp pin voltage ripple induced from the output voltage ripple ( through the internal error amplifier). the c f capacitor usually ranges in value from 10 pf to 100pf. for certain applications, a phase-lead zero capacitor c pl (in parallel with r fb1 resistor), or a pole-zero pair (c opto and r d ) on the opto pin may help improve the transient performance of the loop. a practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your applica - tion, and tune the compensation network to optimize the per formance. stability should then be checked across all operating conditions, including load current, input voltage range and temperature. lt 8311 8311f
29 for more information www.linear.com/lt8311 applications information picking the opto-coupler the voltage feedback loop, explained earlier, uses an opto-coupler to convey output voltage information from the secondary side to the primary side ( see figure 17). an opto-coupler is used because of its wide prevalence, relatively low cost, and its ability to convey dc signal information over an isolation boundary with potential differences of up to 5000v. the input of an opto-coupler typically consists of an infrared light- emitting diode ( led), while the output is typically a phototransistor. current flowing into the opto-couplers input led, called i f , causes photons to be emitted. these photons cross the opto- coupler s isolation barrier and get collected in the base of the output phototransistor. this photo current, which essentially forms the phototransistors base current, is gained up by the phototransistors ? ( current gain) before flowing out of the opto-coupler, and is called i opto_out . the key parameter of interest in an opto-coupler is the current transfer ratio ( ctr). ctr is typically expressed in units of %, and is calculated as follows: ctr(%) = i opto _ out i f figure 17. typical opto-coupler configuration in a voltage feedback loop 8311 f17 i opto_out i f primary side of voltage feedback loop v cc opto r e primary side secondary side lt8311 opto- coupler isolation boundary r d where i opto_out is the output current of the opto-coupler and i f is the opto-couplers input led current opto-couplers have historically been disliked, and jus- tifiably so , for having ctrs that degrade with operating lifetime, at higher operating temperatures, and at higher input currents (i f ). much of this ctr degradation comes from a reduction in the quantum efficiency of the input led, which is a function of the leds operating current (i f ), operating temperature and operating lifetime. fortunately, led technology has matured over the last couple of decades, and has allowed improvements in opto- coupler performance, a discussion of which is beyond the scope of this data sheet. avago technologies has published documentation showing 3- sigma ctr degradation of no more than 10% over 30 field years of operation for their opto-couplers manufactured with algaas type leds run - ning 5 ma of input current (i f ) at 100% duty cycle, and at 85c ambient temperature. please refer to the application/design notes from opto- coupler vendors such as avago technologies, cel and vishay, to procure further information on opto-couplers. a typically recommended opto- coupler is the ps2801 from california eastern laboratories (cel). lt 8311 8311f
30 for more information www.linear.com/lt8311 applications information opto-coupler design guidance an opto-couplers ctr degradation affects a forward converters voltage feedback loop in two ways: 1. large signal effect: a drop in ctr means that to sus- tain the same output current from the opto-coupler, the input current of the opto- coupler will have to increase. the input current of the opto-coupler is sourced by the lt8311s opto pin. the opto-feedback loop should be designed such that, at the lowest ctr possible, the lt8311s opto pin is not current limited. the maxi - mum current that the lt8311s internal opto-driver can source out of the opto pin is 10 ma. design the system so that, nominally, the opto pin is sourcing 2 ma to 3ma maximum current into the opto-couplers input. 2. small signal effect: a reduction in ctr by 2 x will cause the dc gain and crossover frequency of the for - ward converters voltage feedback loop to drop by 2x, assuming all other parameters are constant. likewise, an increase in ctr by 2 x, assuming no change in other parameters, will cause the dc gain and the crossover frequency of the voltage feedback loop to increase by 2 x. the voltage feedback loop must be designed ensuring that at ctr (max) ( maximum ctr of the opto- coupler), the crossover frequency of the feedback loop stays well within the nyquist frequency of the system (= switching frequency / 2). a good rule of thumb is to design the voltage feedback loops crossover at about 1/10 of the switching frequency for an opto-coupler at the nominal value of ctr. as explained earlier, improvements in opto- coupler technology have allowed ctr changes over the operating lifetime of an opto-coupler to become significantly smaller and well controlled. however, the more challenging design aspect of an opto-coupler is the absolute variation in its ctr over a large sample size and operating temperature range. it is this spread in ctr that must be accounted for when designing an opto-coupler based voltage feedback loop. picking an opto-coupler whose ctr variation is no more than 2 x its nominal value, is typically a good starting point ( see table 1 for a list of opto-couplers with small ctr spreads at room temperature). the following guidelines help calculate initial values for the input and output resistors of the opto-coupler (r d and r e , respectively) for a generic application. the final values for r d and r e should be determined after bread-boarding a system. use figure 16 as a reference when reading the following guidelines: step 1: pick resistors, r1 and r2, that set the inverting gain of the primary-side ics error amplifier. a typical starting value for r1 would be 22 k on the lt3752, and 100k on the lt8310. a typical starting value for r2 would be 33k on the lt3752, and 150k on the lt8310. step 2: calculate the maximum voltage required at the emitter of the opto-coupler's output transistor (v x_max ) to drive the primary-side ics comp or v c pin to the voltage needed to command zero inductor current ( referred to as v c_low in the following equation): v x _ max = v ref 1 + r1 r2 ? ? ? ? ? ? ? v c _ low ? r1 r2 v c_low is approximately 0.7 v for the lt8310, and 1.25v for the lt3752. v ref is 1.6 v for the lt8310 and 1.25v for the lt3752. step 3: pick a maximum opto-coupler output current (i opto_out_high ) in the range of 1 ma to 10 ma. a typical choice for i opto_out_high might be 2.5 ma. now calculate r e to be: r e = v x ? max i opto _ out _ high step 4: estimate the maximum input current ( i f_high ) needed to be sourced into opto- coupler by the lt8311s op to pin, at the opto-couplers minimum ctr (ctr min ): i f _ high = i opto _ out _ high ctr min ensure that i f_high is well within the 10 ma limit that the lt8311s opto pin can source. step 5: estimate the r d value needed for the opto pin to source the i f_high current at the maximum opto pin lt 8311 8311f
31 for more information www.linear.com/lt8311 applications information voltage (v opto(max) ). the opto-couplers input led has a turn-on voltage of 1.2v: r d = v opto(max) ? 1.2v ? 0.5v i f _ high the extra 0.5 v in the equation is margin to account for the opto pin's linear range. the maximum opto pin voltage is 6v ( minimum guaranteed), when the lt8311s v in pin is at 8 v or higher. at lower v in pin voltages, v opto_max is v in C 1.7v. the previous equations show how r d and r e ought to be calculated for large signal characteristics of an opto- coupler-based voltage feedback loop. the final values chosen for r d and r e may need to be tweaked from the values calculated here to achieve a satisfactory compromise between the large and small signal characteristics of the voltage feedback loop. picking soft-start capacitor (c ss ) for output soft-start the operation section explained how the lt8311s ss pin helps with output soft-start at start-up, with output overshoot control during short-circuit recovery, and to prebias the voltage feedback loop during start-up of the lt8311s opto-control scheme. the soft-start capacitor, c ss , is charged by the lt8311s internally trimmed 10a current source at start-up. since the fb pin voltage tracks the ss pin voltage when the voltage on ss is below 1.227v, setting the ss pins slew rate will set the fb pins slew rate, setting the time taken by the output to come up to its regulation voltage. it is important to recognize that the tracking between the ss pins slew rate and the fbs pin slew rate is only valid as long as the lt8311s soft-start of output voltage is slower than the primary - side ic s soft- start of output voltage, as explained in the operation section. by observing this criteria, the following equation applies: ? v out ? t = ? v fb ? t = 10a c ss where c ss is the capacitor from the lt8311s ss pin to gnd, v out is the output voltage of the forward converter, and v fb is the lt8311s fb pin voltage. in steady state, the ss pin voltage is clamped to a maxi- mum of 2v by an internal clamp. lt 8311 synchronous control fundament als catch and forward mosfet selection when selecting the secondary - side synchronous mosfets , it is important to choose the following parameters care - fully to ensure robust operation of the system: maximum drain-sour ce voltage, maximum drain-source current and maximum gate-source voltage. furthermore, to maximize system efficiency, it is important to lower power dissipation in the mosfets by minimizing their on- resistance ( r ds( on) ) and gate charge (q g ). please use the following guidelines to choose appropriate catch and forward mosfets for a specific application: 1. maximum v ds rating the maximum voltage seen on the drain of the catch mos- fet is a function of the maximum input voltage (v in(max) ) of the system, and the transformer turns ratio (n s /n p ). catch mosfet v ds(max) = v in(max) ? n s n p ? margin where margin is a number from 1 to 3 (typically 1.5 to 2), allowing a certain safety margin in the catch mosfets v ds(max) equation. this will account for voltage spikes as- sociated with the leakage inductance of the transformers secondary winding. using a snubber on the drain of the catch mosfet will minimize leakage inductance spikes and allow margin to approach the lower end of its range. the maximum voltage seen on the drain of the forward mosfet is a function of the reset mechanism used on the primary side of the forward converter to reset the transformers magnetic flux. when using active clamp reset: forward mosfet v ds(max) v out 1 ? v out v in(min) ? n s n p where v in( min) is the minimum input voltage of the system, and v out is the forward converters output voltage. note that this equation for the forward mosfets v ds(max) assumes that the primary sides active clamp capacitor (c cl ) is large enough to be treated as a voltage source. lt 8311 8311f
32 for more information www.linear.com/lt8311 applications information in reality, the drain voltage of the forward mosfet will have some bowing over and above the voltage calculated here, associated with the energy shuttled between l mag and c cl during the reset process. for most applications, this bowing can be accounted for by adding a 20% safety margin on the forward mosfets v ds(max) equation. when using resonant reset: forward mosfet v ds(max) v out f sw ? 2 ? l mag ? c rst where f sw is the forward converters switching frequency, l mag is the magnetizing inductance of the transformers primary winding, and c rst is the resonant reset capacitor used on the primary side. unlike the catch mosfet, the v ds(max) equation of the forward mosfet typically does not need to account for leakage inductance voltage spikes. this is because the turn- on and turn-off events of the forward mosfet, typically, do not involve the forward mosfets drain having to dis- sipate large amounts of stored leakage inductance energy. 2. maximum i ds rating most power mosfet data sheets have a rating for continuous- drain current, and pulse- drain current. continuous-drain current is the rms drain current of the catch and forward mosfet, which is a function of the inductor current, and the duty cycle at which the forward converter is operating. pulse- drain current is the instantaneous maximum drain current seen by the mosfets , and is typically the peak of the inductor current waveform. prior to calculating the maximum continuous-drain cur- rent, it is useful to calculate the minimum, maximum and average duty cycles of the for ward converter: d min = v out v in(max) ? n s n p ? ? ? ? ? ? d max = v out v in(min) ? n s n p ? ? ? ? ? ? d avg = d max + d min 2 where v in(max) and v in(min) are the maximum and mini- mum input voltages of the forward converter. the catch mosfets maximum continuous drain current, i cat_rms , can be calculated as: i cat _ rms = 1 ? d min ( ) ? i load(max) 2 + i ripp(p ? p) 2 12 ? ? ? ? ? ? where d min is the minimum duty cycle of the forward converter, i load(max) is the maximum output load current of the forward converter, and i ripp(p-p) is the peak-to- peak ripple current in the output inductor. i ripp(p-p) is calculated as follows: i ripp(p ? p) = v out ? 1 ? d avg f sw ? l out where d avg is the average duty cycle of the forward con- verter, f sw is the converters switching frequency, and l out is the output inductance value. the forward mosfet s maximum continuous- drain current (i fwd_rms ) is: i fwd _ rms = d max ? i load(max) 2 + i ripp(p ? p) 2 12 ? ? ? ? ? ? both, the forward and catch mosfet should have a peak pulse current rating that is higher than the highest pos- sible peak of the inductor current. this highest possible peak occurs at the maximum load current, and is equal to: i load(max) + i ripp(p ? p) 2 3. maximum v gs rating as explained earlier in the intv cc bias supply section, intv cc is regulated internally to 7 v by the lt8311. by extension, the catch and forward mosfet gates can be driven as high as 7 v when using the lt8311s internal ldo to regulate intv cc . for applications using the lt8311s internal ldo, picking a maximum v gs greater than 10v should suffice. lt 8311 8311f
33 for more information www.linear.com/lt8311 applications information alternatively, the intv cc pin can be overdriven externally up to 16 v. for such applications, picking mosfets with a maximum v gs of 20v should suffice. 4. calculating mosfet losses due to r ds(on) the conduction/ohmic loss associated with the catch and forward mosfet is a function of the mosfets rms cur- rent and its on-resistance. for the vast majority of forward converter applications, which typically have high maximum load currents on the output (5 a or higher), minimizing losses associated with the mosfets r ds(on) will be far more critical than minimizing losses associated with the mosfets gate charge. catch mosfet ohmic loss = (i cat_rms ) 2 ? r cat where r cat is the on-resistance (r ds(on) ) of the catch mosfet. forward mosfet ohmic loss = (i fwd_rms ) 2 ? r fwd where r fwd is the on-resistance (r ds(on) ) of the forward mosfet. 5. calculating q g based loss there are two aspects to the gate charge (q g ) based loss associated with the secondary synchronous mosfets: a. q g based mosfet switching loss: the catch mosfets turn-on and turn-off timings, regardless of preactive or sync mode, are zvs (zero voltage switching ) events. the catch mosfet turns on after the inductor current is already flowing through its body diode. similarly, when the catch mosfet turns off, the inductor current subsequently flows through its body diode. as a result, the voltage across the drain- source terminals of the catch mosfet is small during switching events, resulting in the catch mosfet having insignificant switching loss. the forward mosfets turn-on and turn-off timings, regardless of preactive or sync mode, are zvs (zero voltage switching) and zcs ( zero current switching) events, respectively. the forward mosfet turns on after transformer reset is complete. transformer reset completion is marked by the transformers magnetizing current flowing through the forward mosfets body diode, which allows the forward mosfet to turn on with a small drain-to-source voltage across it. similarly, the forward mosfet typically turns off after the primary- side mosfet has turned off. when the primary-side mosfet turns off, the only current flowing through the forward mosfet is the transformer magnetizing current, which for all intents and purposes, can be as - sumed to be zero. consequently, the forward mosfet has insignificant switching losses. b. q g based converter power loss: as explained earlier in the intv cc bias supply section, there is a power loss incurred in turning on/off the catch and forward mosfets, associated with supplying gate charge (q g ) to the gates of these mosfets. this charge is supplied either by the supply voltage connected to the lt8311s v in pin, when using the internal ldo to regulate intv cc , or by the supply voltage connected to the lt8311s intv cc pin, when driving the intv cc pin externally. in either case, the total loss associated with supplying the gate charge is: power loss = v supp ? (q gcat + q gfwd ) ? f sw where v supp is the supply voltage connected to the lt8311s v in pin when intv cc is internally regulated. alternatively v supp is the supply voltage connected to the lt8311s intv cc pin when intv cc is externally driven. q gcat and q gfwd is the gate charge (q g ) of the catch and forward mosfets, respectively. f sw is the forward converters switching frequency. lt 8311 8311f
34 for more information www.linear.com/lt8311 applications information setting r timer in preactive mode in preactive mode, the timer pin resistor, r timer , pro- grams the maximum period that can elapse between two csw rising edges before a timeout period is triggered. timeout allows the lt8311 to stop all synchronous activ - ity in the event that the primary-side ic stops switching. since csw rising edges represent primary-side switching activity, timeout of csw rising edges is interpreted as stoppage of switchingat which point the lt8311 ceases all secondary-side synchronous switching, and starts its evaluation period. refer to the operation section for de - tails on the evaluation period. secondary-side switching resumes when all conditions within the evaluation period are satisfied. timeout also ensures that switching activity within preactive mode occurs at a frequency that is within preactive modes operating frequency range. as shown in figure 18, every time the csw pin voltage is detected to rise past 1.2 v from a voltage level below C150mv, the lt8311 resets its internal timeout signal. the gate of the catch mosfet, cg turns on ( after some propagation delay) when csw is detected to fall below C150mv. upon cg going high, the catch mosfet turns on and pulls its drain voltage ( csw) close to its source voltage, which is tied to gnd. cg turns off predictively in ccm before an anticipated csw rising edge. if a csw rising edge ( rising from below C150 mv to above 1.2v) does not come along in time to reset the timeout signal, the signal eventually charges up to voltage v ref_timeout and triggers an internal timeout condition. consequently, the lt8311 shuts down all synchronous conduction and starts the evaluation period. the evaluation period ends only when the four conditions listed in the operation section, including the timely reset of the internal timeout signal, are satisfied for three consecutive csw rising edges. upon completion of the evaluation period, the lt8311 restarts synchronous control. figure 18. if timeout is triggered in preactive mode, lt8311 shuts down all synchronous conduction and starts the evaluation period (note: csw's ringing waveform is caused by the inductor current getting to 0a.) 0v 8311 f18 lt8311 internal timeout signal cg predictive turn-off timeout resets only when csw rises past 1.2v, preceded by falling below ?150mv timeout csw (preactive mode) cg time ?150mv 1.2v cg turns on when csw < ?150mv evaluation period v ref_timeout lt 8311 8311f
35 for more information www.linear.com/lt8311 applications information the timer resistor is typically picked to set a timeout period that is 20% higher than the forward converters nominal switching period. timeout = 1.20 f sw where f sw is converter switching frequency in hz. once a timeout period is calculated, the timer pin resis- tor, r timer , can be calculated as follows: r timer (k) ~ 22.1e6 ? timeout where timeout has units of seconds. the relationship between r timer and timeout is not per- fectly linear . table 1 shows r timer values (nearest 1%) for a range of typical forward converter switching frequencies: table 1. r timer 1% resistor values for different forward converter switching frequencies switching frequency (khz) timeout (s) = 1.2 / f sw r timer (k) 100 12 267 150 8 178 200 6 133 250 4.8 107 300 4 88.7 400 3 66.5 500 2.4 53.6 setting the timeout period at 1.2 ? switching period will keep synchronous conduction shut off through frequency foldback in preactive mode, until the switching frequency approaches 80% of its final value. for 100 khz switching applications, this means that the lt8311 is ready for synchronous conduction in preactive mode, at 80khz. although 80 khz is outside the lt8311s data sheet specifi - cations for preactive mode operating frequency range, the ic is designed to operate down to 80 khz to ride through such a frequency foldback event. timeout may also shut off synchronous conduction during csw pulse-skipping events at light output load currents. setting r timer in sync mode in sync mode, the functionality of the timeout period is similar to preactive mode, except that the resetting of the lt8311s internal timeout signal happens every time the sync pin voltage falls below C1.2 v. the goal of the time - out function in sync mode is primarily to limit the catch mosfet on-time in the event that the catch mosfet stays on too long and conducts an unsafe level of reverse-output inductor current (current flows from the output capacitor back towards the drain of the catch mosfet). refer to the section , " configuring csp/csn inputs of the current sense comparators in sync mode, for further informa - tion on what constitutes an unsafe level of reverse-output inductor current. in sync mode, set the timeout period to be 20% longer than the longest switching period of the primary-side ic. typically, the longest switching period of the primary- side ic corresponds to the smallest frequency foldback frequency (f sw_smallest ): timeout = 1.2 f sw _ smallest once a timeout period is calculated, the timer pin resis- tor, r timer , can be calculated as follows: r timer (k) ~ 22.1e6 ? timeout where timeout has units of seconds, and f sw_smallest is in units of hz. configuring csp/csn inputs of current sense comparator in preactive mode the differential input current sense comparator in the lt8311 is used to provide the ic with information about the current in the catch mosfet. connect the csp and csn pins, through series resistors, to the drain and source of the catch mosfet (m cg ), to allow the lt8311 to sense the drain-source voltage of m cg , and make inferences about its current. alternatively, csp and csn can be tied, through series resistors, across a sense resistor which is placed from the source of m cg to ground. as explained earlier in the operation section, the csp and csn pins should be configured, in preactive mode, to trip at zero current in the catch mosfet. since the current comparator internally trips at 66 mv, and the csp pin sources 40a, lt 8311 8311f
36 for more information www.linear.com/lt8311 applications information placing 1%, 1.65 k resistors in series with csp and csn should allow the lt8311 to trip with approximately zero volts across the catch mosfet. note that the current comparator has a propagation delay of 100 ns nominally, so the time taken from the current comparator getting tripped to the catch mosfet turning off is about 100ns. during this 100 ns, the current in the output inductor can reverse and flow from the drain-to-source of the catch mosfet. if negative current flow in m cg is not desired, the csp pin series resistor can be chosen to trip at a positive value of source-to-drain catch mosfet current. the fol - lowing equation allows calculation of the resistor (r csp ) to be placed in series with the csp pin for a desired value of catch mosfet trip current (i trip ): r csp = 66mv ? i trip ? r sns 40a where r sns is the r ds(on) of the catch mosfet when the csp and csn pins are connected directly across the drain- source terminals of the catch mosfet. alternatively, r sns is the sense resistor in the source of the catch mosfet if the csp/csn pins are connected directly across the sense resistor. once the resistor in series with the csp pin (r csp ) is decided, place an identical resistor in series with the csn pin. configuring csp/csn inputs of the current sense comparator in sync mode the lt8311 is typically operated in sync mode when the forward converter needs to be operated in fcm ( forced continuous mode). in sync mode, the lt8311 receives synchronous control signals on its sync pin, through a pulse transformer, from the primary-side ics s out pin. connecting the lt8311s csp/csn pins across the catch mosfets drain and source, in sync mode, is done to protect the catch mosfet from conducting too large a reverse inductor current at light load. the following guidelines offered (steps 1 to 5) may be used to determine an appropriate catch mosfet reverse current trip point (v trip ): step 1 : determine the worst- case negative inductor current value during regular fcm operation, which will likely happen at the smallest frequency foldback frequency, highest v in , and at 0 a load. an easy way to determine this is to run the forward converter with the lt8311 working in sync mode and keeping the csp/csn pins shorted to gnd. observing the inductor current waveform on an oscilloscope at start-up, with v in at its maximum value, and the load at 0 a, can quickly give the user an idea of the worst-case negative inductor current value (i catch_fet ) during regular start-up operation. this will set a lower bound on the csp/csn trip point (v trip minimum): v trip minimum = |i catch_fet | ? r ds(on) where r ds(on) is the on-resistance of the catch mosfet, and i catch_fet is the worst-case magnitude of negative inductor current ( current flowing from drain to source of catch mosfet) during fcm operation at startup. step 2: pick a trip point (v trip ) that allows some margin from the value calculated in step 1. typical margin might be 20%, thereby setting a trip point of: v trip = 1.2 ? v trip minimum step 3: determine the selected catch mosfets single pulse avalanche energy rating (e as in mj) from the mos- fets data sheet and its drain-source break down voltage (v br(dss) in v). step 4: make sure that the chosen csp/csn trip voltage does not allow so much negative current in the catch mosfet, such that when the catch mosfet turns off, its avalanche energy rating ( based on the following equation) is violated: v trip (in volts) < r ds(on) ? 2 ? e as ? (1.3 ? v br(dss) ? v out ) (1.3 ? v br(dss) ? l out ) ? ? ? ? ? ? ? ? where, e as (joules) = catch mosfets single-pulse avalanche energy rating. v br(dss) ( v) = catch mosfets drain-source break down voltage rating. lt 8311 8311f
37 for more information www.linear.com/lt8311 applications information r ds(on) () = catch mosfets on-resistance rating from the mosfets data sheet. v out (v) = forward converters output voltage in steady- state. l out (h) = output inductor. if the v trip voltage is too large, causing the catch mos- fets avalanche energy rating to be violated, then go back to steps 1 and 2, or pick a different mosfet, until the avalanche energy experienced by the mosfet in the application is within its data sheet specified soa. step 5: upon selecting the appropriate trip point, the series resistors , r csp and r csn , may be determined based on the following equation: r csp = r csn = 66mv ? v trip 40a connect r csp between the csp pin and the catch mos- fets drain , and r csn between the csn pin and the catch mosfets source. preactive mode synchronous control preactive mode general guidelines the following guidelines are meant to summarize the connections and operating conditions typically needed to set up the lt8311s synchronous control in preactive mode. while these guidelines are meant to serve as a starting point, they are not a substitute for bench evalua - tion. ultimately, each application that uses the lt8311s preactive mode scheme must be evaluated for its specific requirements, and the ic must be configured accordingly. 1. bias up v in and intv cc as per data sheet recommenda- tions. 2. place a minimum of 2.2 f ceramic capacitor from the v in pin to gnd. 3. place a minimum of 4.7 f ceramic capacitor from the intv cc pin to gnd. 4. tie the pmode and sync pins to 0v. 5. configure r timer to set a timeout period that is 20% higher than the steady-state switching period of the forward converter. 6. connect the csw and fsw pins, through 2 k ceramic resistors, to the drains of the catch and forward mos - fet, respectively . keep the connection as short in length as possible. 7. connect the csp and csn pins, each through a 1.65k resistor, directly across the drain-source terminals of the catch mosfet for v ds sensing. a small 10 pf filter capacitor may be required across the csp and csn pins to filter out external noise that couples in. 8. connect cg and fg to the gates of the catch and for - ward mosfet , respectively, with connections that are as short as possible. once synchronous control is up and running: 9. ensure that the voltage at the csw and fsw pins does not exceed the abs max rating of 150 v. if the csw or fsw pin voltage exceeds 150 v, you may need to use a rc snubber on the drain of the catch and/or the forward mosfet. 10.if the catch mosfet current trip point is causing the inductor current to reverse ( flowing from output back to the drain of the catch mosfet) at light loads, re- configure the csp/csn trip point to trip at a slightly positive value of source-to-drain current in the catch mosfet. this typically involves increasing the csp and csn series resistors to a value greater than 1.65k. 11.if the catch mosfets current trip point does not seem consistent, and the catch mosfets turn-off edge seems to show jitter at the trip current, the filter capacitor across the csp and csn pins may need to be adjusted. note that typically, the fb pin will be connected through a resistor divider network to the output voltage, when using the lt8311 as part of a voltage feedback loop. lt 8311 8311f
38 for more information www.linear.com/lt8311 applications information sync mode synchronous control picking the pulse transformer and high pass filter in sync mode, the lt8311 determines the turn-on/off timings of the catch and forward mosfets based on voltage signals on its sync pin. figure 7 in the operation section shows a typical circuit used to communicate syn - chronous control signals from the primary-side ics s out pin to the lt8311s sync pin. this circuit utilizes a pulse transformer ( t2 in figure 7) to provide isolation between the primary and secondary sides, and a high pass filter (r sync and c sync ). c sync blocks dc signals from being applied directly to t2. eliminating the dc component of the s out signal, through the highpass filter ( r sync and c sync ), allows the sync pin signal to go positive or negative at the rising and falling edges of s out , as shown in figure 19. positive and negative signals of equal magnitudes and duration allow equal positive and negative volt-seconds to be maintained on transformer t2, preventing any net magnetizing current build-up. appropriate values of r sync and c sync must be chosen to satisfy all of the following criteria: 1. the r sync ? c sync time constant must be large enough to allow a sufficiently long pulse width to be generated on the sync pin with sufficient overdrive voltage. this is shown in figure 19 where t1 must be at least 50 ns at a sync voltage of 2v ( or greater over drive) to trip the sync comparators. using this constraint, the equation below sets a limit on the minimum r sync ? c sync product required: ? r sync ? c sync v 50ns 1? ? n 2v v max ? where v max is the maximum s out voltage, as shown in figure 19. 2. r sync must be small enough to ensure that the sync signal is sufficiently damped. an underdamped sync signal can cause ringing large enough to cause false triggering of the sync detection comparators, which may lead to improper secondary-synchronous control. the equation used to calculate r sync for optimal damping is given by: r sync f 1 2 ? _ ? l m c sync where _ is the damping factor and should typically be chosen to be about 1. l m is the magnetizing inductance of the pulse transformers primary winding. choosing l m to be larger allows the damping factor to increase, so it would be wise to choose a pulse transformer with a larger primary winding inductance to increase the damping of the sync signal. smaller r sync values also reduce the sensitivity of the highpass filter to stray signals ( parasitic magnetic fields) that may couple in. figure 19. positive and negative sync edges are generated on the rising and falling edges of s out , respectively. the lt8311 requires pulse width time, t1, to be at least 50ns (typical) with the sync pin voltage at 2v (or greater overdrive) to trigger the internal sync detect comparators. 2v t1 0v 0v 8311 f19 s out sync time v max v max ?2v t1 ?v max lt 8311 8311f
39 for more information www.linear.com/lt8311 applications information 3. r sync must be large enough to limit the amount of source/sink current required each time a positive or negative sync pin voltage signal is generated. the s out pins gate drivers offer limited source current capability; r sync must be large enough to ensure that this constraint in current-drive is not violated. for instance, the lt3752s s out drivers are rated for a maximum current of about 100ma. this results in: r sync v max 100ma v max is the s out gate driver high voltage, which is typically about 8v to 12v for the lt3752. the following steps can be used as guidelines to calculate r sync and c sync values: step 1: choose pulse transformer. a typically recom- mended choice is the pe-68386nl from pulse electronics. step 2: determine the primary-side ics maximum s out signal magnitude , v max ( see figure 19). this sets the maxi - mum magnitude of the signal on the lt8311s sync pin. step 3: guess a capacitance value for c sync . a good starting value might be between 220pf and 1nf. step 4: pick r sync based on constraint shown in the following equation: 1 2 ? l m c sync ? ? ? ? ? ? r sync max 50ns c sync ? ? 1 ? in(2v / v max ) ? ? ? ? , v max i max ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? where i max is the maximum current source/sink capability of the primary-side ics s out pin ( lt3752s maximum capability is about 100ma and lt8310 s maximum current capability is about 300 ma). it is recommended to design for an i max that is lower than the maximum recommended source current specified, to allow for design margin over process and temperature. if the r sync calculation in step 4 yields an unreasonable resistance value, go back to steps 1 to 3, and change either l m , v max , or c sync . recalculate r sync in step 4 until all criteria are satisfied. design example in a lt3752-lt8311 forward converter design, pulse transformer pe-68386nl is chosen for communication of lt3752 s out signals, through a highpass filter, to the lt8311s sync pin. step 1: this transformer has a magnetizing inductance of l m = 785h. step 2: lt3752s v max = 12v. step 3: choose c sync = 220pf step 4: designing for i max = 70 ma, l m = 785 h, c sync = 220 pf, v max = 12 v, results in the following calculation for r sync : 944 r sync max {127, 171} conclusion in this example, r sync = 560 is chosen along with c sync = 220 pf as the highpass filter to be used along with pulse transformer, pe-68386nl to communicate the lt3752s s out signals to the lt8311s sync pin. lt 8311 8311f
40 for more information www.linear.com/lt8311 typical applications 18v to 72v, 12v/8a active clamp isolated forward converter 8311 ta02 lt3753 uvlo_vsec ovlo ivsec rt tos tblnk tao tas gnd ss1 ss2 intv cc aout fb sync s out r4 71.5k c4 1f c3 0.47f v in 18v to 72v v in r2 5.9k r3 1.82k r5 31.6k 240khz r7 34k comp isensen oc out isensep r6 49.9k c10 2.2f 100v ?? c9 100nf c6 4.7f r13, 2k r12 6m r11 100 c7 1f 1k r8 100k r9 100k r22 154k lt8311 fsw csw csp cg csn opto gnd comp sync pmode ss fb v in intv cc pgood timer v out 12v/8a v out l1 6.8h d2 r19, 1.78k r20, 1.5k fg r16, 2k r25 100k r24 20k r26 11.3k c19 22f 2 r17, 2k r18, 1.78k c20 470f c18 68pf c12 15nf r21 2.94k c14 1f c15 4.7f c16 2.2f c17 2.2nf r14 10k c11 100nf 4:4 t1 r23 100k 2.2nf ps2801-1 c5 10pf + c1 4.7f 3 r1 100k d1 d3 t1: champs b45r2-0404.04 t2: cel ps2801 l1: champs pqr2050-08 m1: infineon bsc077n12ns3 m2: ir irf6217pbf m3: fairchild semi. fdms86101dc m4: infineon bsc077n12ns3 d2: central semi. cmmr1u-02 d3: diodes inc. sbriu150 m3 m1 m4 m2 efficiency and power loss at v in = 48v load current (a) 1 efficiency (%) 90 92 94 88 86 5 3 7 9 84 82 96 power loss (w) 8 10 12 6 4 2 0 14 8311 ta02b efficiency power loss v in = 48v lt 8311 8311f
41 for more information www.linear.com/lt8311 typical applications 18v to 72v, 12v/12.5a, 150w active clamp isolated forward converter r4 49.9k r5 22.6k r3 1.82k r6 7.32k r7 34k r8 71.5k r9 31.6k r23 100k r24 100k r10 2.8k r11 10k t1: champs g45r2_0404.04d t2: bh electronics l00-3250 t3: pulse pe-68386nl l1: champs g45ah2-0404-d4 d1, d2, d3: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.006 r16 10k r18 0.15 r17 499 c10 2.2f c9 2.2f intv cc v aux m5 zvn4525e6 si2325ds d3 t2 d2 d1 m1 bsc077n12ns3 m2 m3 fdms86101 bsc077n12ns3 r25 100 r12 1.1k r26 1k 2.2nf c2 0.33f c3 22nf ps2801-1 c4 22nf c5 4.7f c11 2.2f c13 22f 16v 2 c24 2.2nf 250v v out 12v 12.5a c14 470f 16v c12 4.7f c17 220nf 8311 ta03a c18 68pf c19 4.7nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.9k r1 100k uvlo_v sec lt3752 sync c7 100nf c8 15nf t1 4:4 m4 r20 499k r29 13.7k l1 6.8h r30 100k r31 11.3k csn fg fsw cg csw r21 100 r22 100 r38 20k + ?? ?? ? ? ? c1 4.7f 100v 3 v in 18v to 72v gnd ovlo hfb d4 c28 68pf load current (a) 0 efficiency (%) 96 94 92 90 88 86 63 8311 ta03b 15129 24v in 48v in 72v in efficiency vs load current lt 8311 8311f
42 for more information www.linear.com/lt8311 typical applications 18v to 72v, 12v/12.5a, 150w no-opto, active clamp isolated forward converter r4 49.9k r5 22.6k r3 1.82k r6 7.32k r7 34k r8 60.4k r9 31.6k r10 2.8k r11 10k t1: champs g45r2_0404.04d t2: bh electronics l00-3250 t3: pulse pe-68386nl l1: champs g45ah2-0404-d4 d1, d2, d3: bas516 d4: central semi cmmr1u-02 r13 560 v aux v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.006 r16 10k r18 0.15 r17 499 c10 2.2f c9 2.2f intv cc v aux m5 zvn4525e6 d3 t2 d2 d1 m1 bsc077n12ns3 fdms86101 r12 1.1k 2.2nf c2 0.33f c3 22nf c4 22nf c5 4.7f c11 2.2f c13 22f 16v 2 v out 12v 12.5a c14 470f 16v c12 4.7f 8311 ta04a c6 220pf t3 t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.9k r1 100k uvlo_v sec lt3752 sync c7 100nf c8 15nf t1 4:4 r20 499k l1 6.8h csn fg fsw cg csw r21 100 r22 100 + ?? ?? ? ? ? c1 4.7f 100v 3 v in 18v to 72v gnd ovlo hfb si2325ds m3 m4 bsc077n12ns3 m2 c24 2.2nf 250v r38 20k d4 load current (a) 0 v out (v) 14.0 13.5 13.0 12.5 12.0 11.0 10.5 11.5 10.0 42 8311 ta04b 12 8 10 6 v in = 70v v in = 60v v in = 48v v in = 36v v in = 20v load current (a) 0 efficiency (%) 96 94 92 90 88 86 63 8311 ta04c 15129 24v in 48v in 72v in v out vs load current (no-opto) efficiency vs load current lt 8311 8311f
43 for more information www.linear.com/lt8311 typical applications 150v to 400v, 12v/16.7a, 200w active clamp isolated forward converter r4 95.3k r5 40.2k r3 2.94k r6 13k r7 100k r8 124k r9 78.7k r23 22k r24 22k r10 22k r11 10k t1: champs lt80r2-12ac-3124005 t2: wrth 750817020 t3: pulse pe-68386nl l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.022 r18 0.15 r17 499 r35 374k r36 374k c10 4.7f c9 10f intv cc v aux intv cc m5 bsp300 d3 t2 d2 m1 ipd65r25oc6 ipd60r1k4c6 m3 m2 r25 100 r12 806 r26 1.2k 2.2nf c2 0.47f c3 0.22f ps2801-1 c4 3.3nf c5 4.7f c11 2.2f c13 33f 16v 4 c24 10nf 250v v out 12v 16.7a c14 330f 16v c12 4.7f c17 1f 8311 ta05a c18 100pf c19 22nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc v aux timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.76k r1 499k r34 499k uvlo_v sec lt3752-1 sync rjk0653dpb 2 t1 31:5 c20 10f d5 m4 fdms86200 3 r20 432k r29 5.11k l1 15h r30 100k r31 11.3k csn fg fsw cg csw r21 100 d4 r22 100 r38 10k r38 0.002 c27 120pf + ?? ?? ? ? ? d1 r16 4.2 c1 2.2f 630v v in 150v to 400v gnd ovlo hfb cathode anode acpl-w346 v ee v out v cc c21 0.22f c8 47nf 630v c15 10nf 630v r19 402 c28 68pf load current (a) 0 efficiency (%) 96 95 94 93 92 90 89 91 88 85 87 86 52.5 8311 ta05b 17.5 10 12.5 15 7.5 v in = 150v v in = 250v v in = 350v v in = 400v efficiency vs load current lt 8311 8311f
44 for more information www.linear.com/lt8311 typical applications 150v to 400v, 12v/16.7a, 200w no-opto, active clamp isolated forward converter r4 95.3k r5 40.2k r3 2.94k r6 13k r7 100k r8 107k r9 78.7k r10 22k r11 10k t1: champs lt80r2-12ac-3124005 t2: wrth 750817020 t3: pulse pe-68386nl l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.022 r18 0.15 r17 499 r35 374k r36 374k c10 4.7f c9 10f intv cc v aux intv cc m5 bsp300 d3 t2 d2 m1 ipd65r25oc6 ipd60r1k4c6 m3 m2 r12 806 2.2nf c2 0.47f c3 0.22f c4 3.3nf c5 4.7f c11 2.2f c13 33f 16v 4 v out 12v 16.7a c14 330f 16v c12 4.7f v aux 8311 ta06a c6 220pf t3 t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.76k r1 499k r34 499k uvlo_v sec lt3752-1 sync rjk0653dpb 2 t1 31:5 c20 10f d5 m4 fdms86200 3 r20 432k l1 15h csn fg fsw cg csw + ?? ?? ? ? ? d1 acpl-w346 r16 4.2 c1 2.2f 630v v in 150v to 400v gnd ovlo hfb cathode anode v ee v out v cc c21 0.22f c8 47nf 630v c15 10nf 630v r19 402 r38 0.002 r21 100 r22 100 c27 120pf c24 10nf 250v d4 r38 10k load current (a) 0 v out (v) 14.0 13.5 13.0 12.5 12.0 11.5 10.0 11.0 10.5 42 8311 ta06b 18 8 1210 14 16 6 v in = 150v v in = 250v v in = 350v v in = 400v load current (a) 0 efficiency (%) 96 95 94 93 92 90 89 91 88 85 87 86 52.5 8311 ta06c 17.5 10 12.5 15 7.5 v in = 150v v in = 250v v in = 350v v in = 400v v out vs load current (no-opto) efficiency vs load current lt 8311 8311f
45 for more information www.linear.com/lt8311 typical applications r4 95.3k r5 40.2k r3 2.94k r6 13k r7 100k r8 124k r9 78.7k r23 22k r24 22k r10 22k r11 10k t1: champs lt80r2-12ac-3124005 t2: wrth 750817020 t3: pulse pe-68386nl t4: ice gt05-111-100 l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.022 r18 0.15 r16 10k c23 3.3nf r17 499 r35 374k c22 220nf r37 100 r36 374k c10 4.7f c9 10f intv cc v aux d1 c21 470pf m5 bsp300 d3 t2 t4 d2 m1 ipd65r25oc6 ipd60r1k4c6 m3 m2 r25 100 r12 806k r26 1.2k 2.2nf c2 0.47f c3 0.22f ps2801-1 c4 3.3nf c5 4.7f c11 2.2f c13 33f 16v 4 v out 12v 16.7a c14 330f 16v c12 4.7f v aux c17 1f 8311 ta07 c18 100pf c19 22nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 5.76k r1 499k r34 499k uvlo_v sec lt3752-1 sync rjk0653dpb 2 t1 31:5 c20 10f d5 m4 fdms86200 3 r20 432k r29 5.11k l1 15h r30 100k r31 11.3k csn fg fsw cg csw + ?? ?? ? ? ? c1 2.2f 630v v in 150v to 400v gnd ovlo hfb c8 47nf 630v c15 10nf 630v r19 402 ?? r21 100 r22 100 r38 0.002 c27 120pf c24 10nf 250v d4 r38 10k c28 68pf load current (a) 0 efficiency (%) 96 95 94 93 92 90 89 91 88 85 87 86 52.5 8311 ta07b 17.5 10 12.5 15 7.5 v in = 150v v in = 250v v in = 350v v in = 400v 150v to 400v, 12v/16.7a, 200w, active clamp isolated forward converter (using gate drive transformer for high side active clamp) efficiency vs load current lt 8311 8311f
46 for more information www.linear.com/lt8311 typical applications 75v to 150v, 24v/14a 340w active clamp isolated forward converter (using gate drive transformer for high side active clamp) r4 93.1k r5 53k r3 5.76k r6 10k r7 80.1k r8 82.5k r9 52.3k r23 22k r24 22k r10 22k r11 10k t1: champs lt80r2-12ac-1006 t2: wrth 750817020 t3: pulse pe-68386nl t4: ice gt05-111-100 l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 r28 3.16k r27 100k v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.0075 r18 0.15 r16 10k c23 3.3nf r17 499 r35 102k c22 220nf r37 100 r36 102k c10 4.7f c9 10f intv cc v aux d1 c21 470pf m5 bsp300 d3 t2 t4 d2 m1 ipb200n25n3 irfl214 m3 m2 r25 100 r12 806 r26 1.2k 2.2nf c2 0.47f c3 0.22f ps2801-1 c4 3.3nf c5 4.7f c11 2.2f c13 22f 25v 4 v out 24v 14a c14 470f 25v c12 4.7f c17 0.33f v aux 8311 ta08a c18 100pf c19 22nf c6 220pf t3 c16 1f t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 6.04k r1 6.98k r34 698k uvlo_v sec lt3752-1 sync bsc047n08ns3 2 t1 10:6 c20 10f d5 m4 1pb072n15n3g r20 365k r29 5.11k l1 15f r30 100k r31 5.36k csn fg fsw cg csw + ?? ?? ? ? ? c1 2.2f 250v v in 75v to 150v gnd ovlo hfb c8 15nf 250v c15 4.7nf 250v r19 1k ?? r21 100 r22 100 r38 0.003 c27 120pf c24 10nf 250v d4 r38 10k c28 68pf load current (a) 0 efficiency (%) 96 95 94 93 92 91 86 90 89 88 87 2.5 8311 ta08b 15 7.5 10 12.5 5 v in = 75v v in = 100v v in = 125v v in = 150v efficiency vs load current lt 8311 8311f
47 for more information www.linear.com/lt8311 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe20(16) (cb) tssop rev 0 0512 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 18 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package variation: fe20(16) 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1924 rev ?) exposed pad variation cb lt 8311 8311f
48 for more information www.linear.com/lt8311 ? linear technology corporation 2014 lt 0314 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8311 related parts typical application part number description comments lt3752/lt3752-1 active clamp synchronous forward controllers with internal housekeeping controller ideal for medium power 24v, 48v and up to 400v input applications lt3753 100v input, active clamp synchronous forward controller ideal for medium power 24v and 48v input applications ltc3765/ltc3766 isolated synchronous no-opto forward controller chip set direct flux limit, multiphase capable ideal for medium power 24v and 48v input applications ltc3722-1/ ltc3722-2 synchronous phase modulated full bridge controllers ideal for high power 24v and 48v input applications lt3748 isolated flyback controller 5v v in 100v, no-opto required msop-16 (12) lt8300 100v micropower isolated flyback converter monolithic no-opto with integrated 260ma switch, tsot-23 lt3511/lt3512 100v isolated flyback converters monolithic no-opto with integrated 240ma/420ma switch, msop-16(12) 75v to 150v, 24v/14a 340w no-opto, active clamp isolated forward converter r4 93.1k r5 53k r3 5.76k r6 10k r7 80.1k r8 75k r9 52.3k r10 22k r11 10k t1: champs lt80r2-12ac-1006 t2: wrth 750817020 t3: pulse pe-68386nl t4: ice gt05-111-100 l1: coilcraft agp2923-153 d1: central semi cmr1u-10 d2, d3, d5: bas516 d4: central semi cmmr1u-02 r13 560 v aux sync v in gnd fb lt8311 pgood r14 2k r15 0.0075 r18 0.15 r16 10k c23 3.3nf r17 499 r35 c22 220nf r37 100 r36 c10 4.7f c9 10f intv cc v aux d1 c21 470pf m5 bsp300 d3 t2 t4 d2 m1 1pb200n25n3 irfl214 m3 m2 r12 806 2.2nf c2 0.47f c3 0.1f c4 3.3nf c5 4.7f c11 2.2f c13 22f 25v 4 v out 24v 14a c14 470f 25v c12 4.7f 8311 ta08a c6 220pf t3 t ao t as t os t blnk ivsec rt ss1 ss2 hcomp fb comp opto intv cc timer ss comp csp pmode intv cc intv cc sout i sensen i sensep out v in aout hi sense hout oc r2 6.04k r1 6.98k r34 698k uvlo_v sec lt3752-1 sync bsc047n08ns3 2 t1 10:6 c20 10f d5 m4 1pb072n15n3g r20 432k l1, 15h csn fg fsw cg csw + ?? ?? ? ? ? c1 2.2f 250v v in 75v to 150v gnd ovlo hfb c8 15nf 250v c15 4.7nf 250v r19 1k ?? r21 100 r38 0.003 r22 100 c27 120pf c24 10nf 250v d4 r38 10k load current (a) 0 v out (v) 28 27 26 25 24 20 23 22 21 2 8311 ta08b 16 12 14 6 8 10 4 v in = 75v v in = 100v v in = 125v v in = 150v load current (a) 0 efficiency (%) 96 95 94 93 92 91 86 90 89 88 87 2.5 8311 ta08c 15 7.5 10 12.5 5 v in = 75v v in = 100v v in = 125v v in = 150v v out vs load current (no-opto) efficiency vs load current lt 8311 8311f

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